Spectrum Digital, Inc
2-2
TMS320C6713 DSK Module Technical Reference
2.1 CPLD (Programmable Logic)
The C6713 DSK uses an Altera EPM3128TC100-10 Complex Programmable Logic
Device (CPLD) device to implement:
• 4 Memory-mapped control/status registers that allow software
control of various board features.
• Control of the daughter card interface and signals.
• Assorted "glue" logic that ties the board components together.
2.1.1 CPLD Overview
The CPLD logic is used to implement functionality specific to the DSK. Your own
hardware designs will likely implement a completely different set of functions or take
advantage of the DSPs high level of integration for system design and avoid the use
of external logic completely.
The CPLD implements simple random logic functions that eliminate the need for
additional discrete devices. In particular, the CPLD aggregates the various reset
signals coming from the reset button and power supervisors and generates a global
reset.
The EPM3128TC100-10 is a 3.3V (5V tolerant), 100-pin QFP device that provides
128 macrocells, 80 I/O pins, and a 10 ns pin-to-pin delay. The device is
EEPROM-based and is in-system programmable via a dedicated JTAG interface
(a 10-pin header on the DSK). The CPLD source files are written in the industry
standard VHDL (Hardware Design Language) and included with the DSK.
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