HOT-613 User's Manual 23
PCI Burst Write Combining
When enabled will increase the efficiency of PCI bus by combining serval CPU to PCI
write cycles into one.
PCI-To-DRAM Pipeline
When enabled will increase the bandwidth of the path between the PCI and the DRAM to
enhance the PCI bus efficiency and DRAM accessing
CPU-To-PCI Write Post
When enabled will increase the efficiency of the PCI bus and speed up the execution in the
processor.
CPU-To-PCI IDE Posting
When disabled, the CPU to PCI IDE posting cycles are treated as normal I/O write
transactions. When enabled will have the I/O write cycles posted.
System BIOS Cacheable
This item allows the user to set whether the system BIOS F000~FFFF areas are cacheable
or non-cacheable.
Video RAM Cacheable
This item allows the user to set whether the video BIOS C000~C7FF areas are cacheable
or non-cacheable.
8 Bit I/O Recovery Time
The recovery time is the length of time, measured in CPU clocks, which the system will
delay after the completion of an input/output request. This delay takes place because the
CPU is operating so much after than the input/output bus that the CPU must be delayed to
allow for the completion of the I/O.
This item allows you to determine the recovery time allowed for 8 bit I/O. Choices are
from NA, 1 to 8 CPU clocks.
16-Bit I/O Recovery Time
This item allows you to determine the recovery time allowed for 16 bit I/O. Choices are
from NA, 1 to 4 CPU clocks.
Memory Hole At 15M-16M
In order to improve performance, certain space in memory can be reserved for ISA cards.
This memory must be mapped into the memory space below 16 MB.
DRAM Fast Leadoff
When enabled, system will reduce the number of CPU clocks allowed before reads and
writes to DRAM are performed.
