Motherboard Description
SY-K7VEMPRO
9
1-9 CHIPSET
VT8361
The KLE133 chip set consists of the VT8361 system controller (552 pin
BGA) and the VT82C686B PCI to ISA bridge (352 pin BGA). The system
controller provides superior performance between the CPU, DRAM and
PCI bus with pipelined, burst, and concurrent operation.
The VT8361 supports four banks of DRAMs up to 1GB. The DRAM
controller supports standard, Synchronous DRAM (SDRAM), in a flexible
mix / match manner. The Synchronous DRAM interface allows zero wait
state bursting between the DRAM and the data buffers at 100/133 MHz.
The four banks of DRAM can be composed of an arbitrary mixture of
1M/2M/4M/8M/16M/32MxN DRAMs.
The VT8361 system controller also supports full AGP v2.0 capability for
maximum bus utilization including 1x/2x/4x mode transfers, SBA (Side
Band Addressing), Flush/Fence commands, and pipelined grants. An eight
level request queue plus a four level post-write request queue with
thirty-two and sixteen quad words of read and write data FIFO’s
respectively are included for deep pipelined and split AGP transactions. A
single-level GART TLB with 16 full associative entries and flexible
CPU/AGP/PCI remapping control is also provided for operation under
protected mode operating environments. Both Window 95 VxD and
Windows 98 /Windows 2000 mini port drivers are supported for
interoperability with major AGP-based 3D and DVD- capable multimedia
accelerators.
The VT8361 supports two 32-bit 3.3/5V system buses (one AGP and one
PCI) that are synchronous/ pseudo-synchronous to the CPU bus. The chip
also contains a built-in bus-to-bus bridge to allow simultaneous concurrent
operations on each bus. Five levels (double words) of post write buffers
are included to allow for concurrent CPU and PCI operation. For PCI
master operation, forty-eight levels (double words) of post write buffers
and sixteen levels (double words) of prefetch buffers are included for
concurrent PCI bus and DRAM/cache accesses. The chip also supports
Summary of Contents for SY-K7VEMPRO
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