SOYO SY-K7AIA, User Manual

Page: 66 / 88

BIOS Setup Utility SY-K7AIA
62
CHIPSET FEATURES SETUP (Continued)
CHIPSET
FEATURES Setting Description Note
32
SDRAM PH
Limit
1,4,32,64
This option specifies the number of
consecutive Page-Hit requests to
allow before choosing a non-Page-
Hit request.
8 SDRAM Idle
Limit
0,8,12,16,
24,32,48
This option specifies the number of
idle cycles to wait before
precharging an idle bank.
8 SDRAM Trc
Timing Value
3,4,5,6,7,
8
This option specifies the minimum
time from activate to activate of the
same bank.
3 SDRAM Trp
Timing Value
2,3
This option specifies the delay from
precharge command to activate
command.
5 SDRAM Tras
Timing Value
2,3,4,5,6,
7
This option specifies the minimum
bank (SRAS[2:0]#) active time.
3
SDRAM CAS
Latency
2,3
This option specifies the delay from
JSCAS [2:0]# to data valid.
2 SDRAM Trcd
Timing Value
1,2,3,4
This option specifies the delay from
the activation of a bank to the time
that a read or write command is
accepted.
10%
(Down) Default Spread
Spectrum
Modulated
-0.5%
(Down)
When using Spread Spectrum
Modulated 10% (Down) or -0.5%
(Down) for FCC or DOC testing.