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44
TA-F501ES
164
FSRATE
I
L/R sampling clock signal (44.1 kHz) input terminal
165
SUB-U DATA
I
Serial data input from the sub system controller
166
NO USE
—
Not used (Open)
167
EEPROM SDA
I/O
Two-way data bus with the EEPROM
168
EEPROM SCL
O
Serial data transfer clock signal output to the EEPROM
169, 170
+/– JOG1,
I
Jog dial pulse input terminal Not used (Open)
+/– JOG2
171, 172
PAGE JOG1,
I
Jog dial pulse input terminal Not used (Open)
PAGE JOG2
173
MAIN MENU JOG1
I
Jog dial pulse input terminal Not used (Open)
174
MAIN MENU JOG2
I
Clear signal output to the fluorescent indicator tube
175
VSS
—
Ground
176
VCC
—
Power supply (+3.3V)
Pin No.
Pin Name
I/O
Pin Description
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9
9
2
8
9
4
2
9
8
TEL 13942296513
9
9
2
8
9
4
2
9
8
0
5
1
5
1
3
6
7
3
Q
Q
TEL 13942296513 QQ 376315150 892498299
TEL 13942296513 QQ 376315150 892498299