STR-ZA1000ES/ZA2000ES/ZA3000ES
92
Pin No.
Pin Name
I/O
Description
138
FLAG3
-
Not used
139
MLBDAT
I/O
Two-way media local bus data terminal Not used
140
MLBDO
O
Media local bus data output terminal Not used
141
VDD_EXT
-
Power supply terminal (+3.3V) (for I/O)
142
MLBSIG
I/O
Two-way media local bus signal terminal Not used
143
VDD_INT
-
Power supply terminal (+1.1V) (for core)
144
TRST
I
Test reset signal input terminal (for JTAG)
145
MLBSO
O
Media local bus signal output terminal Not used
146
EMU
O
Emulation status signal output terminal
147 to
150
DATA0 to DATA3
I/O
Two-way data bus with the SD-RAM
151
TDO
O
Test data output terminal (for JTAG)
152
DATA4
I/O
Two-way data bus with the SD-RAM
153
VDD_EXT
-
Power supply terminal (+3.3V) (for I/O)
154, 155
DATA5, DATA6
I/O
Two-way data bus with the SD-RAM
156
VDD_INT
-
Power supply terminal (+1.1V) (for core)
157
DATA7
I/O
Two-way data bus with the SD-RAM
158
TDI
I
Test data input terminal (for JTAG)
159
SDCLK
O
Clock signal output to the SD-RAM
160
VDD_EXT
-
Power supply terminal (+3.3V) (for I/O)
161 to
163
DATA8 to DATA10
I/O
Two-way data bus with the SD-RAM
164
TCK
I
Test clock signal input terminal (for JTAG)
165 to
168
DATA11, DATA12,
DATA14, DATA13
I/O
Two-way data bus with the SD-RAM
169
VDD_INT
-
Power supply terminal (+1.1V) (for core)
170
DATA15
I/O
Two-way data bus with the SD-RAM
171
SDWE
O
Write enable signal output to the SD-RAM
172
SDRAS
O
Row address signal output to the SD-RAM
173
RESET
I
Reset signal input from the system controller “L”: reset
174
TMS
I
Test mode selection signal input terminal (for JTAG)
175
SDCAS
O
Column address signal output to the SD-RAM
176
VDD_INT
-
Power supply terminal (+1.1V) (for core)