![Sony STR-DA7100ES - Fm Stereo/fm-am Receiver Service Manual Download Page 38](http://html.mh-extra.com/html/sony/str-da7100es-fm-stereo-fm-am-receiver/str-da7100es-fm-stereo-fm-am-receiver_service-manual_416748038.webp)
38
STR-DA7100ES
DIGITAL BOARD IC2054 MB91F355APMT-A70ES-X110 (MAIN SYSTEM CONTROLLER)
Pin No.
Pin Name
I/O
Description
1, 2
BASS JOG1,
I
Jog dial pulse input from the rotary encoder (for BASS)
BASS JOG2
3, 4
TREB JOG1,
I
Jog dial pulse input from the rotary encoder (for TREBLE)
TREB JOG2
5
SVOL LAT (A90)
-
Not used
6
TUNER LAT
O
Serial data latch pulse signal output to the tuner unit
7
TUNER DO
I
Serial data input from the tuner unit
8
TUNED
I
Tuned detection signal input from the tuner unit
9
STEREO
I
FM stereo detection signal input from the tuner unit
10
RDS DATA
I
RDS serial data input from the tuner unit (AEP model only)
11
DATA0
I
Read data input from the digital audio interface receiver
12
DSP RESET
O
System reset signal output to the DSP “L”: reset
13
DSP (LAT)
O
Serial data latch pulse output to the DSP
14
DSP SPICLK
O
Serial data transfer clock signal output to the DSP
15
DSP MISO
I
Serial data input from the DSP or flash memory
16
DSP MOSI
O
Serial data output to the DSP or flash memory
17
VSS
-
Ground terminal
18
VCC
-
Power supply terminal (+3.3V)
19, 20
DSP BCFG0,
-
Not used
DSP BCFG1
21
SF CPU CE
O
Chip enable signal output for the flash memory
22
SF DSP MAS
I
Master/slave selection signal input terminal “H”: DSP is master
23
96/24
-
Not used
24
T/A XCS
O
Chip select signal output to the lip sync adjust
25
T/A SO
I
Serial data input from the lip sync adjust
26
T/A XRST
O
System reset signal output to the lip sync adjust “L”: reset
27
MAIN DO
O
Serial data output to the PCM/PWM processor
28
MAIN CLK
O
Serial data transfer clock signal output to the PCM/PWM processor
29
SUB-U RESET
O
System reset signal output to the sub system controller “L”: reset
30
DIR XMODE
O
System reset signal output to the digital audio interface receiver “L”: reset
31
DIR CE
O
Chip enable signal output to the digital audio interface receiver
32
DIR DO
I
Serial data input from the digital audio interface receiver
33
DIR ERROR
I
PLL lock error signal and data error flag input from the digital audio interface receiver
34
DIR CKST
I
Clock select signal input from the digital audio interface receiver
35
VSS
-
Ground terminal
36
VCC
-
Power supply terminal (+3.3V)
37
AD/DA RESET
O
System reset signal output to the A/D converter and D/A converter “L”: reset
38
DAC LAT
O
Serial data latch pulse signal output to the D/A converter
39
DAC OUT
I
Serial data input from the D/A converter
40
AD (SB) RESET
O
System reset signal output to the A/D converter (for surround back) “L”: reset
41
ADMIX LAT (A90)
-
Not used
42
PDMIX LAT (A90)
-
Not used
43
RF ERR (A90)
-
Not used
44
MUTE
O
System muting on/off control signal output terminal
45
DAVS
-
Ground terminal
46
DAVC
-
Power supply terminal (+3.3V)
47 to 49
NO USE
-
Not used
50 to 52
AD KEY1 to AD KEY3
I
Front panel key input terminal (A/D input)
53, 54
NO USE
-
Not used