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MDS-JB980
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• IC201 CXD2664R (DIGITAL SERVO SIGNAL PROCESSOR/DIGITAL SIGNAL PROCESSOR) (BD BOARD)
Description
Pin No.
Pin Name
I/O
Not used. (open)
Track jump detection signal output to the system control
In the state of executire command signal output
Not used. (open)
Power supply pin (+2.6 V)
Serial data signal input from the system control
Serial clock signal input from the system control
Serial latch signal input from the system control
Ground pin
Serial reading data signal output to the system control
Internal status (SENSE) output to the system control
Reset signal input from the system control
“L”: Reset
Subcode Q sync (SCOR) signal output to the system control
Digital In U-bit CD format or MD format subcode Q sync (SCOR) signal output to the
system control
Laser power switching signal input from the system control
“H”: Recording, “L”: Playback
Interrupt status signal output to the system control
Recording data signal output enable input from the system control
Power supply pin (+3.3 V)
System clock signal input (Fixed at “L”.)
System clock signal input (Input terminal during OSCN:“H” )
Internal oscillating circuit control signal input
Ground pin
System clock frequency setting
(Fixed at “H”.)
Digital audio signal input (Optical input)
Digital audio signal input (USB input)
Digital audio signal output (Optical output)
Serial data signal input
LR clock signal input
Serial data bit clock signal input
Power supply pin (+2.6 V)
Ground pin
Data input from the A/D converter
Data output to the D/A converter
LR clock signal output for the A/D and D/A converter
Bit clock signal output to the A/D and D/A converter
256Fs clock signal output (Not used.)
Write enable signal output for DRAM
Read enable signal output for DRAM
Power supply pin (+3.3 V)
Ground pin
DRAM address output (Not used.) (Open)
Data input/output for DRAM
* O (3) for 3-state output in the column I/O
MNT0 (FOK)
MNT1 (SHCK)
MNT2 (XBUSY)
MNT3 (SLOC)
VDC0
SWDT
SCLK
XLAT
VSC0
SRDT
SENS
XRST
SQSY
DQSY
RPWR
XINT
XT
VDIO0
OSCI
OSCO
OSCN
VSIO0
XTSL
DIN0
DIN1
DOUT
DATAI
LRCKI
XBCKI
VDC1
VSC1
ADDT
DADT
LRCK
XBCK
FS256
XWE
XOE
DRVDD0
DRVSS0
A11
D3
D0
D2
D1
O
O
O
O
—
I
I
I
—
O (3)
O (3)
I
O
O
I
O
O
—
I
I/O
I
—
I
I
I
O
I
I
I
—
—
I
O
O
O
O
O
O
—
—
O
I/O
I/O
I/O
I/O
