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3-1.

System Block Diagrams

The playback type Mini Discs belonging to the first thru 4th generations have their respective systems composed of the

blocks illustrated below.

(1)

1st Generation [MZ-2P]

Fig. 3-1. First Generation Mini Disc System Block Diagram

(2)

2nd Generation [MZ-E2]

Fig. 3-2. 2nd Generation Mini Disc System Block Diagram

ATRAC(L)

CXD2527

4M DRAM

SYSTEM CONTROLLER

EFM

ACIRC

CXD2525

RF AMP.

CXA1381

OPTICAL BLOCK

KMS-130

ADIP

CXA1380

SHOCK
PROOF

CXD2526

SERVO

CXA1602

DRIVE

MPC1718

ATRAC(R)

CXD2527

AUDIO

OUTPUT

D/A CONV.

AK4501

4M DRAM

SYSTEM CONTROLLER

EFM

ACIRC

CXD2525

RF AMP.

CXA1381

ADIP

CXA1380

SHOCK
PROOF

CXD2526

SERVO

CXA1602

DRIVE

MPC1718

AUDIO

OUTPUT

ATRAC

CXD2531

OPTICAL BLOCK

KMS-200

D/A CONV.

SM5853

Summary of Contents for MZ-E30

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Page 17: ... 1 NEWTECHNICALTHEORY FOR SERVICING MZ E30 OPERATION MANUAL PORTABLE MINI DISC PLAYER ...

Page 18: ...STEM CONTROL 6 1 Detection Switch 27 6 2 Key Input Detection of Control Buttons 28 6 3 Control of APC Circuit and Laser Power 30 7 Playback Circuit 7 1 Outline of Playback Circuit 32 7 2 Playback Operations 32 7 3 Digital DBB and Mute Circuit 33 8 Servo Circuit 8 1 Outline of Servo Circuit 39 8 2 Intermittent Operations of Servo 40 8 3 Focus Search and Disc Discrimination 40 8 4 Focus Servo Circui...

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Page 21: ...loyed while jointly using the principal LSI with a recorder playback unit The MZ E30 however employs an newly developed LSI for the exclusive use of playback which has especially main functions such as shock proof ATRAC decoding EFM decoding and ACIRC decoding The principal LSI in the fourth generation are outlined below µPD63730GC DSSP digital servo EFM decoder ACIR decoder DRAM controller ADIP d...

Page 22: ... Generation MZ E2 Fig 3 2 2nd Generation Mini Disc System Block Diagram ATRAC L CXD2527 4M DRAM SYSTEM CONTROLLER EFM ACIRC CXD2525 RF AMP CXA1381 OPTICAL BLOCK KMS 130 ADIP CXA1380 SHOCK PROOF CXD2526 SERVO CXA1602 DRIVE MPC1718 ATRAC R CXD2527 AUDIO OUTPUT D A CONV AK4501 4M DRAM SYSTEM CONTROLLER EFM ACIRC CXD2525 RF AMP CXA1381 ADIP CXA1380 SHOCK PROOF CXD2526 SERVO CXA1602 DRIVE MPC1718 AUDIO...

Page 23: ...System Block Diagram 4M DRAM SYSTEM CONTROLLER EFM ACIRC DIGITAL SERVO CXD2535 RF AMP CXA1981 DRIVE MPC17A38 AUDIO OUTPUT OPTICAL BLOCK KMS 201 SHOCK PROOF ATRAC CXD2536 D A CONV CS4330 4M DRAM EFM ACIRC SHOCK PLOOF ATRAC DIGITAL SERVO µPD63730 SYSTEM CONTROLLER RF AMP SN761050 DRIVE MPC17A55 AUDIO OUTPUT OPTICAL BLOCK ODX 01 D A CONV AK4314 ...

Page 24: ...ed in the next stage is of low power consumption type in which a mute function is incorporated The system controller serves to control the RF amplifier and the power supply circuit while processing a digital signal and controlling the digital servo together with the DSP digital servo In addition functions to detect a key in and a remote control signal and to control and drive the LCD are also avai...

Page 25: ... System Controller n DSP digital servo WRITE mode Various function data in each digital servo DSSP and SERVO and PLL mode setting data and electronic volume setting data DSP digital servo n System Controller READ mode Error data in each servo and SubQ ADIP cluster and sector information From the system controller to the RF amplifier SBUS data are transferred similarly to the case of DSP digital se...

Page 26: ...commander to the system controller since the receiving data differ in transmission rate etc by type of remote control To transmit data the clock timed with such data is also transmitted normally at a time In the MZ E30 however clock information etc are previously transmitted based on which the controller in the interior of remote control has a function of generating a clock Only a single line for ...

Page 27: ...ontroller is limited to data only but free from Bit 3 D C as shown in Fig 4 5 The DSP digital servo has an SBUS terminal employed as an output port only during the bit period for which data are being output In any other section the DSP digital servo has high impedance Fig 4 5 Timing of Reading onto System Controller from DSP digital servo ...

Page 28: ... to Pin ª MCK in the sled motor control IC803 is used as the master clock for the controller located inside And the bit clock BCK and L R clock LRCK both output to the D A converter are used as the timing signal for the audio data output from the ATRAC block in the DSP digital servo For details refer to 7 2 Playback Operations A frequency of 4 fs which is output from Pin CK176 in the DSP digital s...

Page 29: ...l output if the STOP mode should last for about 10 seconds which varies with an optical block position and or with a mode As a result the power will also stop being supplied to each component To startup on the other hand a wakeup circuit will start up when a operation button located in the remote commander or in the unit is pressed This will cause the step up circuit to start operating so that the...

Page 30: ...RST thereby causing each IC to start operating The frequency of 176 kHz 4 fs fs 44 1 kHz obtained with a frequency of 384 fs available at X301 divided by 96 enters Pin CLK from the DSP digital servo IC601 Thus a switching operation continues so that the step up circuits 1 and 2 will have their respective Drives OSC1 and OSC2 switched over to an external clock 4 fs If the voltage of 2 8V VC fluctua...

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Page 34: ...less will cause the MZ E30 to be put into the STOP mode with Message LoBATT blinking on the remote commander display In approximately 5 seconds a sleep signal will be output from Pin ª SLEEP in the system controller so that the power supply circuit will stop operating Upon wakeup meanwhile Pin in the system controller will change from L to H at the timing shown Fig 5 6 Battery Voltage Monitor Circ...

Page 35: ...e capacitor connected to Pin 7 CRST outputs the RESET signal from Pin 8 XRST to main ICs such as system controller IC801 and DSP digital servo IC601 at the delayed timing shown in the figure Fig 5 7 RESET Circuit and RESET Signal Timing 1 2 VC RESET 2 7 V 6 ms 0 0 2 8 V from SERVO DRIVER IC551 pin VB1 VC IC901 DC DC CONVERTER 10 1 GND 7 CRST C903 8 XRST XRESET 9 IC801 SYSTEM CONTROLLER 30 RESET IC...

Page 36: ...etection switch is performed in this unit by alternately switching the internal gain and laser power settings of the RF amplifier during focus search and detecting at which of these settings the focus turns ON Details of differentiation of the disc are provided in 8 3 Focus Search and Disc Differentiation As this unit uses a single voltage and does not have a recharge function it is not mounted wi...

Page 37: ... input to the key input Pin 8 SET KEY of the system controller when a operation button is pressed When power supply to each part starts after wake up 2 8V VC from Pin VSTB is supplied to R808 47 kΩ via the switch inside the DC DC converter IC901 When a operation button is pressed in this state a dividing voltage determined by R808 47 kΩ and the resistor corresponding to that operation button is in...

Page 38: ...ontroller When a remote commander button is pressed in this state the matrix resistor corresponding to that button and a dividing voltage and R905 are connected in parallel form and the voltage shown in Table 6 2 is input to Pin 7 of the system controller Table 6 2 Key Input Voltage During Operations of Remote Commander Reference Values Fig 6 3 Key Input Circuit of Remote Commander Pin 7 of IC801 ...

Page 39: ...nnected between the monitor diode anode and GND input to Pin PD IN and fed back to the first stage amplifier to control the laser power A constant current circuit is composed by feeding back the voltage decreased by the R506 resistor 4 7 Ω connected to the emitter of the LD drive so that the driving current does not change even when the power supply voltage changes The ON OFF of the laser driving ...

Page 40: ...ion is not used in this unit intended exclusively for playback As the optimum read power differs between the playback only disc and MO disc the disc is differentiated by focus search performed immediately after the unit is started The duty ratio of the PWM wave output from Pin of the system controller is controlled so that 0 6 mW power is obtained if the disc is a playback only disc and 0 8 mW pow...

Page 41: ...3 MHz obtained EFM demodulation is performed in the next stage In the ACIRC decoder data errors are detected and corrected and the data is then written in the DRAM via the RAM controller The accumulated data is compressed to approximately 1 5 according to the transfer command from the system controller and periodically sent to the ATRAC decoder block In the ATRAC decoder block the compressed data ...

Page 42: ...igital DBB Dynamic Bass Boost and mute circuit The D A converter IC301 incorporates a digital DBB function which is switched ON OFF using the DBB switch S301 connected to Pin DBB0 and Pin DBB1 Low bands are boosted using the digital signal When Pin is set to H at the reference level 12 dB signal is boosted by about 3 5 dB for 100 Hz When Pin is set to H it is boosted by about 8 5 dB When DBB is tu...

Page 43: ... disc is played back only the spindle servo in the servo circuit differs from when the playback only disc is played back In the case of the playback of the playback only disc the measured period of the EFM frequency divided signal obtained from the RF signal is used In the case of the MO disc that of the frequency divided signal obtained from the ADIP signal recorded in the groove area is used In ...

Page 44: ...Discrimination Fig 8 3 Focus Search Previous Model Compared to the current CD discs as the reflection rate of the MO disc is low 15 to 30 the difference between the pseudo reflected light on the disc surface polycarbonate board surface of the side where signals are read and the light reflected from the MO media side is small making it difficult for the IC to differentiate between the two As a resu...

Page 45: ...e gain again sets the laser power of the low reflection rate disc MO 0 8 mW and focus search down to top is performed Part B of Fig 8 4 4 If focus is imposed here the disc is determined to be a low reflection rate disc MO after which the tracking servo turns ON and pit groove differentiation is performed This is performed by simultaneously switching the I J pit and I J groove of the RF signal outp...

Page 46: ...o IC601 is incorporated with an A D converter which converts the ABCD signal and the FE signal to 7 bit data at sampling frequencies of 22 05 kHz fs 2 and 88 2 kHz 2 fs respectively The focus error signal is then subject to servo calculation in the DSSP digital servo signal processor block converted to the 88 2 kHz PWM wave and used to control the focus coil via the servo driver IC551 and LPF low ...

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Page 51: ... VDD PD O LD SNS PD IN PD I EXT IN IF IE ID IC IB IA VJ VI OFC C1 OFC C2 EQ 1 EQ 2 EQ 3 SBUS SCK RESET DVA1 D VDD OFTRK ABCD Focus Error ADIP ADIP BPF FE and TE T COUNT 26 25 34 35 38 36 29 31 32 30 33 28 19 18 8 43 20 47 46 5 21 22 24 17 39 41 42 46 44 40 48 23 11 APC 12 13 15 14 16 i v conversion Power supply Thermometer Remote control i v conversion i v conversion i v conversion i v conversion ...

Page 52: ... REXT2 BPFC0 BPFC1 ADIP T COUNT EXT IN DFCT OFTRK 35 34 33 32 31 30 29 28 27 26 25 48 47 46 45 44 43 42 41 40 39 38 37 RF OUT MIRR VTH EQ 3 AGND EQ 2 EQ 1 AVDD OFC C1 OFC C2 VREF2 OUT VREF OUT A GND 13 14 15 16 17 18 19 20 21 22 23 24 RESET DGND SCK SBUS DVDD REXT1 VTEMP DVA1 LD VDD LD SNS LD DRV PD O SN761050A ...

Page 53: ...ource setting resistor Tracking error output Off track detection input A B C D output Focus error output RF output Mirror comparator threshold setting RF amp phase shifter Analog GND RF EQ external constant 2 RF EQ external constant 1 Analog Vdd DC canceler external capacitor 1 DC canceler external capacitor 1 Reference voltage output GND reference 1 2V Reference voltage output GND reference 1 2V ...

Page 54: ... 58 10 2 DSP Digital Servo µPD63730GC DSP digital servo for MD playback Built in ATRAC decoder for playback Digital servo EFM decoder and ACIRC decoder functions 51 75 25 1 76 100 50 26 uPD63730GC ...

Page 55: ... Monitor I O etc AC LRCK FLAG EFM ACIRC Decoder SubQ ADIP Decodeer 8 EBA DSSP ABCD T COUNT DEFECT OFTRK FE TE ABDC VDD ADC RF VREF ADIP RF PLCK EFM PLL ADIP PLL EFM ADIP TE FE ECC DATA SOREQ SBR XI XO MCK 2 MCK RESET SINT SCK SBUS TEST M0CK M1CK M00 3 M10 3 ERFLAG CRCF EFM PLCK ADIP DATA ADPLCK VSS VDD ADC VRB VRT SBW SBA SBD 8 8 2nd MSB EFM DATA A B S DATA ATDT 12 54 55 61 59 63 21 22 23 24 11 12...

Page 56: ...VSS BCK AUDATA LRCK EMP VDD XBUSY SINT SCK SBUS RESET VDD VDD DRA3 DRA2 DRA1 DRA0 DRA4 DRA5 DRA6 DRA7 DRA8 DRA10 DRA11 XRAS DRA9 XOE2 XOE XCAS DRD2 DRD3 VSS XWE2 XWE DRD1 DRD0 VDD VSS MI0 MI1 MI2 MI3 MICK MOCK MO0 MO1 MO2 MO3 VDD PLCK EFM ADPLCK ADIP DATA TEST CRCF ERFLAG FON FOK ID3 ID2 ID1 ID0 VDD ADC VREF RF FE ABCD TE ADIP VRT VRB VSS ADC T COUNT DEFECT OFTRK VSS TFOUT TROUT FROUT FFOUT CK176 ...

Page 57: ... signal output DRAM access status Power supply Emphasis output for DAC ON when H L R clock output Audio data output Bit clock output Ground Digital output 1 4 divided output of MCK 1 2 divided output of MCK Ground Input output direction switching of MCK L output H input Crystal oscillation input 384 fs 16 93 MHz Crystal oscillation output Master clock input output I O I I I I I I I I I I I O O O O...

Page 58: ...ut Monitor output Monitor output Monitor output Power supply PLL clock input output PLL input output ADIP PLL clock input output ADIP PLL demodulation input output Test CRC flag Error flag FON signal FOK signal SSB code setting input SSB code setting input SSB code setting input SSB code setting input I O I O I O O O I O I O O O O O O O O O O O O O O O O O I O I O I O I O O O O O O O I O I O I O I...

Page 59: ... 63 10 3 Servo Driver MPC17A55FTA MD CD player motor driver system power supply 54 54 1 18 36 19 55 72 MPC17A55FTA ...

Page 60: ...4 VM4 FO4 RO4 RI4 FI4 RI3 FI3 CLPF RGDN VREG VREG CONT L1 GNDDCC1 GNDDCC1 L1 VO VO GND DCC2 L2H VB2 VB1 VB1 VB VB PWM D1 D0 OE PI1 PI2 GNDPS PO2 VPS2 PO1 VPS1 HIU HIV HIW VC VC VG L2L VG VG VG VG D0 or D1 VG VG VG VG VC VC VC VC int OE int STB VC PWM Control PWM Control Slep Up Down Power SW Decoder Slep Up Down Pre driver Slep Up Pre driver Power SW Pre driver H Bridge Control Pre driver H Bridge...

Page 61: ... the phase detection comparator W phase output of the phase detection comparator Normal rotation input of the phase detection comparator Three phase driver power supply Three phase driver U phase output and reverse rotation input of the phase detection comparator Power GND for the three phase driver Three phase driver V phase output and reverse rotation input of the phase detection comparator Powe...

Page 62: ... 3 control input H bridge driver 4 control input H bridge driver 4 control input Driver output enable control input Regulator circuit output Regulator circuit output enable control input Regulator circuit GND Regulator circuit reference voltage filter Control circuit power supply Control circuit GND Pre driver circuit power supply DC DC PWM signal input Operation mode setting I O _ O _ O _ O _ O _...

Page 63: ...operations of the power MOSFET are set as shown in Truth Table 2 PWM and PWMB in the table indicate outputs with the same phase and opposite phase with the 176 kHz PWM signal input to the PWM terminal are obtained respectively a 176 kHz duty 70 fixed pulse is also output to the L2L terminal Truth Table 1 Power Switch Truth Table 2 Power Switch D0 L L H H D1 L H L H M1 OFF ON OFF OFF M2 OFF OFF ON ...

Page 64: ...fferent ON resistors and logic are incorporated in four channels These set into the standby state when Int OE is L and their outputs are fixed at L regardless of the input logic When Int OE becomes H these drivers starts operating The ON resistor is defined as the sum of the top and bottom Truth Table 2 Bias control block D0 or D1 L H H H OE X X L H VC X Below 1 4V Above 2 1V Above 2 1V Int STB L ...

Page 65: ...esistors It sets into the standby state when Int OE is L and sets into the operating state when the signal becomes H The ON resistors M11 and M12 are 1 0 Ω typ and M13 and M14 are 0 5 Ω typ Truth Table HIU X L L L L H H H H HIV X L L H H L L H H HIW X L H L H L H L H HOU L L Z L L H H Z L HOV L L L H Z Z L H L HOW L L H Z H L Z L L Int OE L H H H H H H H H Int OE L H H PI1 2 X L H PO1 2 L L H 31 2...

Page 66: ...nal As described in the bias control section as Int STB contains hysteresis against VC when VC rises VREG switches from VC to 0 9 VC at 2 1V When it falls VREG switches from 0 9 VC to VC at 1 4V When VREG CONT is L VREG becomes High Z Functions Table VREG CONT X L H L H Fig 6 3 Phase Comparator This comparator is used for detecting the phase of the 3 phase motor driver The IN terminal of one pin i...

Page 67: ... 71 10 4 DC DC Converter MPC1830VMEL Power Supply for System for MD CD Player 1 18 36 19 MPC1830VMEL ...

Page 68: ... 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 SYSTEM CONTROL BANDGAP REFERENCE RESET OSC1 PWM1 MODE SELECT SAW OSC2 STEP UP DC DC CONVERTER SPCK BUFF CHARGE PUMP VB SELECT GND VRMC VRFE INM RF DTC CRST XRST VBMON VC SPCKO SPCK1 C2L C1L VB C1H C2H VG 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 ...

Page 69: ...g capacitor Switching power supply control driver start request output Switching power supply control mode output Switching power supply control mode output Switching power supply control PWM output Stepup converter driver pin Driver output grounding pin Outputs the higher voltage between the VB1 and VB2 inputs Connected to smoothing capacitor Pin connecting 1 cell 1 5V batteries such as Ni cd Ni ...

Page 70: ...when the wake terminal becomes HIGH Latches at the rising edge of Latch 1 to 4 Latches when Latch 5 becomes H from L Latching is set at the falling edge of XWK1 to XWK4 and wake is output At this time the input terminal which had become LOW prohibits the latching of other input terminals from being set until FFCLR becomes HIGH The FFCLR and SLEEP terminals are negated while XRST is LOW XWK1 Wake S...

Page 71: ...en D0 H D1 H or L using VB2 VG VB 2 VC VBH is output with the higher voltage between VB2 and VB1 When XRST is L M1 continues switching until the reference voltage dividing VBH is exceeded to generate VG for starting from VBH SPCKI is negated until XRST becomes H SPCKI is also pulled up to VC VC VC CLK XRST D1 D0 VBH VG VG VBH L M1 SW VC VG VG M1 M2 VC SPCKO SPCK1 CLK XRST INT XRST INT VC VB M2 M1 ...

Page 72: ...he step down mode PWM1 outputs the STARTUP CLK when XRST INT is L The switching power supply control circuit is composed of the error amplifier and comparator The error amplifier extracts the error voltage from the 1 2 reference voltage of VREF and VC and generates PWM from SAW DTC performs the software switching at start and at the same time limits the PWM duty Although the maximum duty is set to...

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