— 55 —
FOK signal output to the system control
“H” is output when focus is on
Track jump detection signal output to the system control
Monitor 2 output to the system control
Monitor 3 output to the system control
Writing data signal input from the system control
Serial clock signal input from the system control
Serial latch signal input from the system control
Reading data signal output to the system control
Internal status (SENSE) output to the system control
Reset signal input from the system control
“L”: Reset
Subcode Q sync (SCOR) output to the system control
“L” is output every 13.3 msec. Almost all, “H” is output
Digital In U-bit CD format subcode Q sync (SCOR) output to the system control
“L” is output every 13.3 msec
Almost all, “H” is output
Laser power switching input from the system control
“H”: Recording, “L”: Playback
Interrupt status output to the system control
Recording data output enable input from the system control
System clock input (512Fs=22.5792 MHz)
System clock output (512Fs=22.5792 MHz) (Not used)
System clock frequency setting
“L”: 45.1584 MHz, “H”: 22.5792 MHz (Fixed at “H”)
+3V power supply (Digital)
Ground (Digital)
Digital audio input (Optical input)
Digital audio output (Optical output)
Data input from the A/D converter
Data output to the D/A converter
LR clock output for the A/D and D/A converter (44.1 kHz)
Bit clock output to the A/D and D/A converter (2.8224 MHz)
11.2896 MHz clock output (Not used)
+3V power supply (Digital)
DRAM address output (Used : CXD2652AR, Not used : CXD2650R)
Ground (Digital)
Output enable output for DRAM (Used : CXD2652AR, Not used : CXD2650R)
CAS signal output for DRAM (Used : CXD2652AR, Not used : CXD2650R)
Address output for DRAM (Used : CXD2652AR, Not used : CXD2650R)
RAS signal output for DRAM (Used : CXD2652AR, Not used : CXD2650R)
Write enable signal output for DRAM (Used : CXD2652AR, Not used : CXD2650R)
* I (S) stands for Schmidt input, I (A) for analog input, O (3) for 3-state output, and O (A) for analog output in the column I/O
• IC121 Digital Signal Processor, Digital Servo Signal Processor, EFM/ACIRC Encoder/Decoder,
Shock-proof Memory Controller, ATRAC Encoder/Decoder, 2M Bit DRAM (CXD2650R or CXD2652AR)
Function
Pin No.
Pin Name
I/O
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29 to 32
33
34 to 38
39
40
41
42
43
44
45
MNT0 (FOK)
MNT1 (SHCK)
MNT2 (XBUSY)
MNT3 (SLOC)
SWDT
SCLK
XLAT
SRDT
SENS
XRST
SQSY
DQSY
RECP
XINT
TX
OSCI
OSCO
XTSL
DVDD
DVSS
DIN
DOUT
ADDT
DADT
LRCK
XBCK
FS256
DVDD
A03 to A00
A10
A04 to A08
A11
DVSS
XOE
XCAS
A09
XRAS
XWE
O
O
O
O
I
I (S)
I (S)
O (3)
O (3)
I (S)
O
O
I
O
I
I
O
I
—
—
I
O
I
O
O
O
O
—
O
O
O
O
—
O
O
O
O
O
