Sony MDS-DRE1, Service Manual

Page: 61 / 77

– 86 –
•
DIGITAL BOARD IC701 DSP56004FJ66 (DSP)
Pin No. Pin Name I/O Function
1 GNDA —
Ground terminal (for EMI control output buffer)
2 MCS0 O
Chip select signal output terminal Not used (open)
3 to 5 MA15 to MA13 O
Address signal output terminal Not used (open)
6 VCCA —
Power supply terminal (+5V) (for EMI address output buffer and EMI control output buffer)
7 MA12 O
Address signal output terminal Not used (open)
8 GNDA —
Ground terminal (for EMI address output buffer)
9 VCCQ —
Power supply terminal (+5V) (for internal logic)
10 GNDQ —
Ground terminal (for internal logic)
11, 12 MA11, MA10 O
Address signal output terminal Not used (open)
13, 14 MA09, MA08 O
Address signal output to the D-RAM (IC702)
15 GNDA —
Ground terminal (for EMI address output buffer)
16 MA07 O
Address signal output to the D-RAM (IC702)
17 VCCA —
Power supply terminal (+5V) (for EMI address output buffer and EMI control output buffer)
18 to 20
MA06 to MA04 O
Address signal output to the D-RAM (IC702)
21 GNDA —
Ground terminal (for EMI address output buffer)
22 to 25 MA03 to MA00 O
Address signal output to the D-RAM (IC702)
26 SCL I
Serial clock signal input from the system controller (IC101)
27 EXTAL I
System clock signal input terminal Bit clock signal input in this set
28 VCCQ —
Power supply terminal (+5V) (for internal logic)
29 GNDQ —
Ground terminal (for internal logic)
30 PINIT I
PLL initialize terminal Not used (fixed at “L”)
31 GNDP —
Ground terminal (for PLL system)
32 PCAP —
Connected to capacitor (for PLL filter)
33 VCCP —
Power supply terminal (+5V) (for PLL system)
34 GNDS —
Ground terminal (for SAI, SHI and ONCE output buffer)
35 SDA I/O
Two-way data bus with the system controller (IC101)
36 RESET I
System reset signal input from the system controller (IC101) “L”: reset
37 MODA/IRQA I
38 MODB/IRQB I
Mode selection terminal Fixed at “H” in this set
39 MODC/NMI I
40 VCCS —
Power supply terminal (+5V) (for SAI, SHI and ONCE output buffer)
41, 42 HA0, HA2 I
Not used (fixed at “L”)
43 HREQ I
Not used (fixed at “H”)
44 GNDS —
Ground terminal (for SAI, SHI and ONCE output buffer)
45 SDO2 O
Enable control signal output to the shift register and latch (IC256, 257)
46 SDO1 O
Serial data output to the shift register and latch (IC256, 257)
47 SDO0 O
Playback serial data output to the CXD8517Q (IC751)
48 VCCS —
Power supply terminal (+5V) (for SAI, SHI and ONCE output buffer)
49 SCKT O
Bit clock signal output to the CXD8517Q (IC751)
50 WST O
L/R sampling clock signal output to the CXD8517Q (IC751)
51 SCKR I
Bit clock signal input from the CXD2537R (IC601)
52 GNDQ —
Ground terminal (for internal logic)
53 VCCQ —
Power supply terminal (+5V) (for internal logic)
54 GNDS —
Ground terminal (for SAI, SHI and ONCE output buffer)
55 WSR I
L/R sampling clock signal input from the CXD2537R (IC601)
56 SDI1 I
Serial data input from the system controller (IC101)