NW-HD5
19
19
NW-HD5
5-2. BLOCK DIAGRAM – MAIN Section (2/2) –
193
IC1001_XCS7
182
IC1001_XRE
185
IC1001_XWE
183
IC1001_XLWR
184
IC1001_XUWR
181
IC1001_WAIT
88
XINTREQG
89 83
XINTREQH
XINTREQU
D0 – 15
D0 – 15
A1 – 20
D0 – 15
IC1003 – IC7001
186
IC1001_XCS0
191
IC1001_XCS5
192
IC1001_XCS6
DATA BUS
A1 – 23
ADDRESS BUS
FLASH MEMORY
IC1101
197 – 207,
16 – 25
38 – 45
IC1001_XUWR
IC1001_XRE
IC1001_XCS0
XRST
106
138
137
LEVEL SHIFT
Q1001
HEADPHONE AMP
IC4301
BEEP
HP_MUTE
HP_LINE_SEL
SREQ
J4301
F4301
+2.4V_AD
RM_GND
/LINE OUT
RM_KEY
RM_TSB
RM_VDD
i
WAKEUP
XRESET
DATA_READY
XINT
SS
SI
SO
SCLK
GDAC_LRCK
GDAC_PCM0
GDAC_BCK
MULTI_SCK
PMC_DTCK
AD_RMKEY
MULTI_SO
REAL TIME CLOCK
IC9503
X9501
32kHz
77
175
151
153
XRESET
SLEEP
FS256
XOUT
CDIF_PCMD
CDIF_XRDE
CDIF_LRCK
CDIF_BCK
A1 – 23
X1002
22.5792MHz
X3001
22.5792MHz
• SIGNAL PATH
: AUDIO
IC3001 – IC7001
MULTI_SIO
A1 – 20
IC1001_XRE
D0 – 15
16 – 25
38 – 45
IC1001_XUWR
(E, Taiwan, Korean, Chinese, Tourist)