9-10
HXCU-100
9-10
2
3
4
5
1
A B C D E F G H
+3.2V
GND
74M-CLK-SDI
023
GND
GND
+3.2V
GND
GND
GND
22
R563
22
RB501
1
2
3
4
5
6
7
8
22
R564
10pF
NM
C505
TP501
0.1uF
C510
0.1uF
C511
0.1uF
C509
0.1uF
C530
470
R513
22
R520
0.1uF
C506
FB501
1k
NM
R512
22
R550
22
R560
2.2k
R511
22
R525
22
R509
10k
R521
22
R529
22
R514
100
R518
0.1uF
C512
10uH
L501
47
RB506
1
2
3
4
5
6
7
8
FB502
22
R528
100
R549
TP502
10uF
C508
47
RB505
1
2
3
4
5
6
7
8
22
R552 NM
220
RB503
1
2
3
4
5
6
7
8
CDCVF2510APWR
IC501
AGND
1
VCC1
2
1Y0
3
1Y1
4
1Y2
5
GND1
6
GND2
7
1Y3
8
1Y4
9
VCC2
10
G
11
FBOUT
12
FBIN
13
VCC3
14
1Y5
15
1Y6
16
1Y7
17
GND3
18
GND4
19
1Y8
20
1Y9
21
VCC4
22
AVCC
23
CLK
24
+3.2V
+3.2V
C513
0.1uF
DPR-RESET_2
007,009,011,017,018
TC7SZ08FU(TE85R)
IC514 (2/2)
3
GND
5
VCC
+3.2V
+3.2V
0.1uF
C514
GND
100k
RB509
12
34
56
78
100
R541
100k
RB519
12
34
56
78
0.1uF
C518
22
R532
0.01uF
C520
GND
+3.2V
+3.2V
47
RB521
1
2
3
4
5
6
7
8
10
+3.2V
100k
RB512
12
34
56
78
GND
0.1uF
C516
220
RB511
1
2
3
4
5
6
7
8
RESET_1968
013,014
GND
GND
2.2k
R531
47k
R537
GND
GND
TC7SZ08FU(TE85R)
IC514 (1/2)
2
1
4
220
RB510
1
2
3
4
5
6
7
8
+3.2V
+3.2V
220
RB520
1
2
3
4
5
6
7
8
DPR-RESET_1
025
GND
47k
R540
GND
47
RB518
1
2
3
4
5
6
7
8
R539
220
RB514
1
2
3
4
5
6
7
8
0.01uF
C521
47
RB516
1
2
3
4
5
6
7
8
47
R538
+3.2V
220
RB513
1
2
3
4
5
6
7
8
+3.2V
47
RB515
1
2
3
4
5
6
7
8
100k
RB507
12
34
56
78
TC7SZ08FU(TE85R)
IC509 (1/2)
2
1
4
GND
47
RB517
1
2
3
4
5
6
7
8
100k
RB508
12
34
56
78
TC7SZ08FU(TE85R)
IC509 (2/2)
3
GND
5
VCC
GND
+3.2V
0.1uF
C515
MST-74M-CLK_in
002
MST-27M-CLK_in
002
CPU_BUS
002
CP-CLK_1
024,025
CPU_I/F
007,011,017,020,022,024,025
GND
+3.2V
0.1uF10V
C523
GND
CP-CLK_2
020
0.8
CL501
22
R526
22
R527
74M-CLK-FPGA-POST
020
74M-CLK-FPGA-ANALOG
024
74M-CLK-PROCYON
022
27M-CLK-PROMPTER
006
27M-CLK-FPGA-MAP
007
10
GND
+3.2V
GND
TC7SET08FU(T5RSOJF)
IC506 (1/2)
2
1
4
TC7SET08FU(T5RSOJF)
IC506 (2/2)
3
GND
5
VCC
10
IIC2-BUS
026
10k
R535
0.1uF
C517
+3.2V
100
R524
AUDIO-RX
017
220
RB504
1
2
3
4
5
6
7
8
AUDIO-RX12-MIC_out
002
AUDIO-RX34-AES_out
002
AUDIO-RX56-INCOM_out 002
AUDIO-TX
007,017
R3112N281A-TR-FA
IC513
CD
5
GND
3
OUT
1
VDD
2
NC
4
GND
FB504
TC7SZ08FU(TE85R)
(1/2)
IC515
2
1
4
0.1uF
C527
+3.2V
GND
TC7SZ08FU(TE85R)
(2/2)
IC517
3
GND
5
VCC
+3.2V
TC7SZ08FU(TE85R)
(1/2)
IC517
2
1
4
0.1uF
C529
TC7SZ08FU(TE85R)
(2/2)
IC519
3
GND
5
VCC
GND
10
R548
10
R547
10k
R546
+3.2V
TC7SZ08FU(TE85R)
(2/2)
IC515
3
GND
5
VCC
0.1uF
C526
GND
+3.2V
10
R561
TC7SZ08FU(TE85R)
(1/2)
IC518
2
1
4
CP-CLK_3
017
100
R542
R543
22
RB502
1
2
3
4
5
6
7
8
GND
GND
74M-CLK-FPGA-MAP
007
27M-CLK-PROCYON
022
27M-CLK-FPGA-POST
020
27M-CLK-FPGA-ANALOG 020,024
27M-CLK-ENCODER
026
0.1uF
C522
0
R510
0
R519
GUARD-GND(MST-27CLK)
002
GUARD-GND(MST-74CLK)
002
2.2k
R555
22
R553
0
R554
+3.2V
GND
FB505
GUARD-GND(HD-Prom-CK)
002
HD-PROMPT-CLK_in
002
AUDIO-TX_in
002
27M-CLK-DA-COMPOSITE 028
47
R559
R544
DPR-RESET_3
020,022,024,026
+3.2V
47k
R558
+3.2V
0.1uF
C528
TC7SZ08FU(TE85R)
(2/2)
IC518
3
GND
5
VCC
GND
CP-CLK_4
007
TC7SZ08FU(TE85R)
(1/2)
IC519
2
1
4
10
R562
CDCVF2510APWR
IC504
AGND
1
VCC1
2
1Y0
3
1Y1
4
1Y2
5
GND1
6
GND2
7
1Y3
8
1Y4
9
VCC2
10
G
11
FBOUT
12
FBIN
13
VCC3
14
1Y5
15
1Y6
16
1Y7
17
GND3
18
GND4
19
1Y8
20
1Y9
21
VCC4
22
AVCC
23
CLK
24
GND
0.1uF
C536
0.1uF
C535
0.1uF
C533
0.1uF
C534
FB506
0.1uF
C537
FB507
10pF
NM
C532
470
R523
1k
NM
R522
GND
0.1uF
C531
TC74VHC245FT(EKJ)
IC505
A1
2
A2
3
A3
4
A4
5
A5
6
A6
7
A7
8
A8
9
OE
19
DIR
1
GND
10
B8
11
B7
12
B6
13
B5
14
B4
15
B3
16
B2
17
B1
18
VCC
20
TC74VHC245FT(EKJ)
IC510
A1
2
A2
3
A3
4
A4
5
A5
6
A6
7
A7
8
A8
9
OE
19
DIR
1
GND
10
B8
11
B7
12
B6
13
B5
14
B4
15
B3
16
B2
17
B1
18
VCC
20
TC74VHC245FT(EKJ)
IC508
A1
2
A2
3
A3
4
A4
5
A5
6
A6
7
A7
8
A8
9
OE
19
DIR
1
GND
10
B8
11
B7
12
B6
13
B5
14
B4
15
B3
16
B2
17
B1
18
VCC
20
TC74VHC245FT(EKJ)
IC507
A1
2
A2
3
A3
4
A4
5
A5
6
A6
7
A7
8
A8
9
OE
19
DIR
1
GND
10
B8
11
B7
12
B6
13
B5
14
B4
15
B3
16
B2
17
B1
18
VCC
20
74M-CLK-DAYTONA-RET
009
GND
NJM2871BF33-TE2
IC520
VIN
5
GND
2
VOUT
4
N_BYP
3
CTL
1
0.1uF
10V
C501
0.1uF
C502
1uF
6.3V
C503
22k
R501
+5V-D
GND
74M-CLK-FF
007,009,020
+3.2V
100k
RB522
12
34
56
78
100k
RB523
12
34
56
78
74M-CLK-FPGA-DEMUX
017
CDCVF2505PWR
IC503
CLKIN
1
1Y1
2
1Y0
3
GND
4
CLKOUT
8
1Y3
7
VDD3.3V
6
1Y2
5
CLK-VIDEO-TRUNK_2
007
10
R565
10
R566
CLK-VIDEO-TRUNK_1
007
10
R556
10
R567
CL502
1.2
27M-CLK-SDI
023
+2.5V
TC7SZ08FU(TE85R)
(1/2)
IC523
2
1
4
CP-CLK_5
022
10
R572
0.1uF
C541
GND
TC7SZ08FU(TE85R)
(2/2)
IC523
3
GND
5
VCC
10k
R573
+2.5V
TC7SZ08FU(TE85R)
(1/2)
IC524
2
1
4
100
R576
PROCYON_PLL_RST
022
47k
R574
+2.5V
100
R575
GND
TC7SZ08FU(TE85R)
(2/2)
IC524
3
GND
5
VCC
0.1uF
C540
+2.5V
TC74LCX138FT(EKJ)
IC511
A
1
B
2
C
3
G1
6
G2A
4
G2B
5
GND
8
Y7
7
Y6
9
Y5
10
Y4
11
Y3
12
Y2
13
Y1
14
Y0
15
VCC
16
10uF
1608
6.3V
C504
47uF
6.3V
3216
C507
+3.3V_DRV
10
(1/10W)
R503
10
(1/10W)
R502
TC7SZ08FU(TE85R)
IC502 (1/2)
2
1
4
TC7SZ08FU(TE85R)
IC502 (2/2)
3
GND
5
VCC
22
R505
22
R504
+3.2V
FB503
GND
0.1uF
C519
AUDIO-TX12-PGM_in
AUDIO-TX-64FS_in
AUDIO-TX56-INCOM_in
AUDIO-TX34-SPARE_in
AU-TX12-PGM
AU-TX34-SPARE
AU-TX56-INCOM
CPU-D1
WR_in
BUS(6)_in
RD_in
CPU-D0
CPU-WR
CPU-A4
BUS(3)_in
CPU-D5
CPU-A2
CPU-A1
BUS(1)_in
ADDR(3)_in
ADDR(0)_in
BUS(7)_in
CS0_in
MST-RESET_in
CPU-D6
CPU-D3
BUS(4)_in
CPU-RD
ADDR(4)_in
BUS(0)_in
CPU-A0
CPU-D4
CPU-D2
BUS(2)_in
CPU-CK_in
ADDR(2)_in
ADDR(1)_in
CPU-D7
CPU-A3
BUS(5)_in
CPU-A2
CPU-A3
CPU-A4
CPU-RD
CS0
SDA_in/out
SDA
SCL
SCL_in
AUDIO-TX-LRCK_in
AU-RX12-MIC
AU-RX34-AES
AU-RX56-INCOM
AU-TX-LRCK
CS_MAP
CS_TORINO
CS_CAFE-T
CS_POST
CS_ANALOG
CS_DEMUX
CS_HBF
CS0
CPU-D5
CPU-D0
CPU-D4
CPU-D3
CPU-D7
CPU-D2
CPU-D1
CPU-D6
CS_ZXCV
AU-TX-64FS
27MHz
4.49 x C(uF)[S]
CPU_I/F
RESET
CLOCK
MST 74MHz
AUDIO I/O
(N-ch_Open_Drain_Output)
from MB
from MB
from/to MB
from/to ENCODER
to MB
from MB
+3.2V
to FPGA-DEMUX(LRCK,64FS)
to FPGA-MAP
(0.02uF-> 90mS)
from MB
HD-PROMPT-CLK
MST-74M
MST-27M
PROCYON
RET-Y/C/F/H FF(near CN)
FPGA(MAP)
DAYTONA RET ENC
GENNUM PS
FPGA(DEMUX)
FPGA(ANALOG)
FPGA(POST)
MST HD-F FF(near CN)
CXD1968*6
TORINO
DAYTONA RET ENC
CAFE-T
DAYTONA MAIN DEC
FPGA MAP
FPGA DEMUX
ZXCV(RST,TRST)
SD CHAR GEN
ENCODER
FPGA POST
FPGA ANALOG
CXD9186(HBF)
FPGA(MAP)
VIDEO-TRUNK-Y/C/F/H FF(near CN)
74/27MHz
FPGA(MAP)
VBS DEC for PROMPTER
GENNUM SDI
PROCYON
FPGA(POST)
FPGA(ANALOG)
ENCODER(CXD9184)
THS5661 D/A for COMPOSITE OUT
+3.3V
MAIN
DEMUX
DAYTONA
MAIN DEC
PROCYON
PLL
SYS CLK
SYS CLK
RET
FF
DAYTONA
RET ENC
CAFE-T
(-05)
PLL
MAP
150mA=>
Pd=0.97x0.15=145.5mW
(MAX:350mW)
Vd=1.7--0.97V
I= 0--150mA
(MAX:90mA@74MHz)
(Vd=0.75V@75mAx2)
(4.25-5.0V)
R533
R534
R530
100
100
100
DPR-300 (5/28)
BOARD NO. 1-879-649-11
HDCU-300_DPR-300_011_5
DPR-300 (5/28)
DPR-300 (5/28)
Summary of Contents for HKCU-FP1
Page 1: ...HD CAMERA CONTROL UNIT HXCU 100 FRONT CONTROL PANEL HKCU FP1 SERVICE MANUAL 1st Edition ...
Page 8: ......
Page 26: ......
Page 60: ......
Page 92: ......
Page 106: ......
Page 191: ...8 1 HXCU 100 8 1 Section 8 Block Diagrams ...
Page 196: ......
Page 226: ......
Page 242: ......
Page 248: ......
Page 294: ......