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HCD-SHAKE5/SHAKE6D
49
IC701 TAS3108DCPR (MOTHERBOARD BOARD (1/9))
IC740 SRC4182 (MOTHERBOARD BOARD (1/9))
MCLK
Input
SAP
Audio DSP Core
Output
SAP
Microprocessor
and
I
2
C Bus Controller
PLL and Clock Management
M
U
X
M
U
X
M
U
X
M
U
X
M
U
X
M
U
X
÷4
Master
SCL
Oversample Clock
N = 0 (Default)
M = 8 (Default)
I
2
C
Master/Slave
Controller
8-Bit
WARP
8051 Microprocessor
OSC
÷2
÷2
÷2
÷2
÷ Z = 2
DEFAULT
÷ X = 1
DEFAULT
÷ Y = 64
DEFAULT
÷10
1/(M+1)
1/2
N
M
U
X
PLL
X 11
20
SCLKIN
19
LRCK
3
XTALI
2
VR_PLL
1
AVSS
4
XTALO
5
MCLKI
6
MCRCK_DV
7
CS0
8
GPIO
9
DVDD
10
DVSS
11
SDIN1
12
SDIN2
13
SDIN3
14
SDIN4
15
SDA1
16
SCL1
17
SDA2
18
SCL2
21
MCLKO
36
PLL2
37
RSRV
38
AVDD
39
GND
35
PLL1
34
PLL0
22
SCLKOUT1
23
SCLKOUT2
24
SDOUT4
25
SDOUT3
26
SDOUT2
27
SDOUT1
28
VR_DIG
29
DVSS
30
DVDD
31
PDN
32
RESET
33
RSRV
P
R
G
L
1
18 OFMT1
17 OWL0
16 OWL1
20 TDMI
19 OFMT0
24 LRCKO
23 SDOUT
26 MODE0
25 BCKO
28 MODE2
27 MODE1
22 VDD
21 DGND
15 RDY
2
RCKI
3
NC
4
SDIN
5
BCKI
6
LRCKI
9
BYPAS
10
IFMT0
11
IFMT1
12
IFMT2
13
RST
14
MUTE
7
VIO
8
DGND
REFERENCE
CLOCK
INTERPOLATION
FILTERS
RE-SAMPLER
DECIMATION
FILTERS
AUDIO
OUTPUT
PORT
AUDIO
INPUT
PORT
RATE
ESTIMATOR
CONTROL
LOGIC
Summary of Contents for HCD-SHAKE5
Page 85: ...MEMO HCD SHAKE5 SHAKE6D 85 ...