![background image](http://html.mh-extra.com/html/sony/hcd-md595/hcd-md595_service-manual_420817080.webp)
80
– RDS IC Board –
22
23
24
25
26
27
28
29
30
31
33
34
35
36
37
38
39
40
41
42
21
20
CPU
INTERFACE
+
–
+
–
+
–
+
–
+
–
+
–
+
–
+
–
32
18
19
17
16
15
14
13
12
10
9
8
7
6
5
4
3
2
1
+
–
+
–
+
–
+
–
+
–
+
–
11
BB
AMP2
BB
AMP1
FIN
AMP2
FIN
AMP1
TONE
AMP2
TONE
AMP1
BASS
AMP2
BASS
AMP1
MIX
AMP2
MIX
AMP1
BUFF
AMP2
BUFF
AMP1
MIC
AMP
VREF
AGND
AVDD
A
A
B
B
BASS BOOST SW
BASS BOOST SW
SURROUND SW
CLK
DVDD
AVDD
OUT2
INBB2
NFBB2
FBB2
VOL IN2
TONE OUT2
FTRE2
NFBAS2
INBAS2
REC OUT2
IN2D
IN2C
IN2B
IN2A
MIC IN
VREFO
AGND
FBAS2
DATA
LATCH
OUT1
DGND
INBB1
NFBB1
FBB1
VOL IN1
TONE OUT1
FTRE1
NFBAS1
INBAS1
REC OUT1
IN1D
IN1C
IN1B
IN1A
SUR C
SUR R
VREFI
FBAS1
REF AMP
1
2
3
4
5
+
–
INTERRUPT SIGNAL
GENERATING BLOCK
RESET SIGNAL
GENERATING BLOCK
+
–
GND
INT
RESET
CD
VCC
COM
COM
ANALOG
DIGIT
AL
RCLK
NC
XO
XI
VSS2
T2
VDD2
T1
QUAL
RDA
T
VREF
MUX
VDD1
VSS1
VSS3
CMP
1
4
3
6
5
8
7
2
14
15
16
13
12 11 10
9
CLOCK
PLL 57kHz
RDS/ARI
COMPARATOR
8th SWITCHED
CAPACITOR
FILTER
ANTI-ALIASING
FILTER
BIPHASE
DECODER
PLL
1187.5Hz
DEFFERENTIAL
DECODER
TEST