Sony HCD-MD515 - Component For Dhcmd515, Service Manual, Page: 60 / 110

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BD (MD) BOARD IC316 M30610MC-109FP (MD SYSTEM CONTROL)
Pin No. Pin Name I/O Function
1 JOG0 I Encoder switch signal input terminal Not used (fixed at “L”)
2 JOG1 I Encoder switch signal input terminal Not used (fixed at “L”)
3,4 I Not used (fixed at “L”)
5 SQSY I Subcode Q sync (SCOR) input from the CXD2652AR (IC121)
6 REMCON I Remote control signal input (fixed at “H”)
7 EMP O De-emphasis control signal output to the AK4520 (IC201)
8 BYTE I External data bus line byte select signal input terminal “L”:16bit “H”: 8bit (fixed at “L”)
9 CNVSS — Ground terminal
10 XIN-T I Sub system clock input terminal Not used (fixed at “L”)
11 XOUT-T O Sub system clock output terminal Not used (pull down)
12 SYSTEM-RST I MD reset signal input from the master controller (IC500)
13 XOUT O Main system clock signal output terminal (7MHz)
14 GND — Ground terminal
15 XIN I Main system clock signal input terminal (7MHz)
16 +3V — Power supply terminal (+3.3V)
17 I Not used (fixed at “H”)
18 AMUTE O Mute control signal output terminal Not used (fixed at “L”)
19 PWR-DWN I Power down detect signal input terminal
20 DQSY I Digital in U-bit CD format subcode Q sync (SCOR) input from the CXD2652SAR (IC121)
21 STB I Stand-by signal input terminal Not used (pull down)
22 DA-RST O D/A converter reset signal output terminal Not used (pull down)
23 XINT I Interrupt status input from the CXD2652AR (IC121)
24 DA-EN O D/A converter enable signal output to the AK4520 (IC201)
25 AD-EN O A/D converter enable signal output to the AK4520 (IC201)
26 MEC-BUSY O Mecha-busy signal output to the master controller (IC500)
27 FLCS O Display clear signal output terminal Not used (pull down)
28 FLCLK O Display data clock signal output terminal Not used (pull down)
29 I Not used (fixed at “L”)
30 FLDATA O Display data signal output terminal Not used (pull down)
31 TXD O MD control data signal output to the master controller (IC500)
32 RXD I MD control data signal input to the master controller (IC500)
33 CLK I MD control data clock signal input to the master controller (IC500)
34 MAS-BUSY I Master-busy signal input from the master controller (IC500)
35 SWDT O Writing data signal output to the CXD2652AR (IC121)
36 SRDT I Reading data signal input from the CXD2652AR (IC121)
37 SCLK O Serial clock signal output to the CXD2652AR (IC121)
38 XLAT O Serial latch signal output to the CXD2652AR (IC121)
39 O Not used (fixed at “L”)
40 DIG-RST O Reset signal output enable signal output to the CXD2652AR (IC121) “L”:reset
41 SENS I Status (SENSE) input from the CXD2652AR (IC121)
42 SCTX O Recording data output enable signal output to the CXD2652AR (IC121)
43 I Not used (fixed at “L”)
44 WRPWR O Laser power selection signal output to the CXD2652AR (IC121) “H”:rec, “L”:play
45 MNT3 I Monitor signal input from the CXD2652AR (IC121)
46 MNT2 I Busy signal input from the CXD2652AR (IC121)
47 MNT1 I Track jump detection signal input from the CXD2652AR (IC121)
48 MNTO I Focus OK signal input from the CXD2652AR (IC121) “L”:NG