71
HCD-LF1
Pin No.
Pin Name
I/O
Description
195
HCS0
O
Chip select signal output to the programmable ROM
196
VDDP
—
Power supply terminal (+3.3V)
197
TRST
I
Reset signal input terminal (for JTAG)
198
TDO
O
Data output terminal (for JTAG)
199
TDI
I
Data input terminal (for JTAG) Not used
200
TMS
I
Mode selection signal input terminal (for JTAG)
201
TCK
I
Clock signal input terminal (for JTAG)
202
RESET
I
System reset signal input from the system controller “L”: reset
203
BUS CLK
O
Not used
204
GND
—
Ground terminal
205
VDD
—
Power supply terminal (+1.8V)
206
HA3
O
Address signal output to the programmable ROM
207
HA2
O
Address signal output to the programmable ROM and address latch
208
GNDP
—
Ground terminal