HBD-E770W
77
• IC Pin Function Description
MB-134 BOARD IC101 CXD9983GG (BD DECODER)
Pin No.
Pin Name
I/O
Description
A1
FESFDO
I
Serial data input terminal for the front-end serial
fl
ash
A3
VOUTD1
-
Not used
A5
VOUTD5
-
Not used
A7
VOUTD9
-
Not used
A9
VOUTD12
-
Not used
A11
VIND0
O
Serial data transfer clock signal output to the digital audio interface receiver
A13
VIND12
I
CSFLAG signal input from the digital audio interface receiver
A15
VIND16
-
Not used
A17
GPIO1
I
Busy request signal input from the system controller
A19
SPDIF
O
Digital audio data output terminal Not used
A21
SPBCK
I
Bit clock signal input from the digital audio interface receiver
A23
AVDD12_27MPLL
-
Power supply terminal (+1.2V)
A25
NS_XTALI
O
System clock signal output terminal (27 MHz)
A27
CH1_M
O
TMDS data (negative) output to the HDMI ARC OUT connector
A29
CLK_M
O
TMDS clock signal (negative) output to the HDMI ARC OUT connector
A31
DACOUT4
O
Not used
A33
DACOUT1
O
Video signal (Pr/Cr) output terminal
A35
VCLK
O
Serial data transfer clock signal output to the system controller
A37
UARXD
-
Not used
A39
ETRXD3
I
Receive data input from the ethernet interface
A41
ETRXD0
I
Receive data input from the ethernet interface
A43
ETRXCLK
I
Receive clock signal input from the ethernet interface
B2
FESFCS
I
Chip select signal input terminal for the front-end serial
fl
ash
B4
VOUTD3
-
Not used
B6
VOUTD7
-
Not used
B8
VOUTD10
-
Not used
B10
VOUTD14
-
Not used
B12
VIND4
O
Reset signal output to the digital audio interface receiver
B14
VIND14
-
Not used
B16
VINHSYNC
-
Not used
B18
GPIO3
O
Power on/off control signal output terminal for the USB section
B20
SPLRCK
I
L/R sampling clock signal input from the digital audio interface receiver
B22
AOBCK
O
Bit clock signal output to the audio section
B24
AVDD12_DMPLL
-
Power supply terminal (+1.2V)
B26
CH2_M
O
TMDS data (negative) output to the HDMI ARC OUT connector
B28
CH0_M
O
TMDS data (negative) output to the HDMI ARC OUT connector
-
Not used
O
Video signal (Pb/Cb) output terminal
I
Serial data input from the system controller
I
Error signal input from the digital audio interface receiver
I/O
Two-way data bus with the ethernet interface
I
Receive data input from the ethernet interface
I
Receive error signal input from the ethernet interface
O
Serial data transfer clock signal output terminal for the front-end serial
fl
ash
O
Serial data output terminal for the front-end serial
fl
ash
-
Not used
C7
VOUTD8
-
Not used
C9
VOUTD11
-
Not used
C11
VOUTD15
-
Not used
C13
VIND11
-
Not used
C15
VIND15
-
Not used
C17
GPIO0
O
Request signal output to the system controller
C19
GPIO2
I
Chip select signal input from the system controller
C21
SPMCLK
I
Master clock signal input from the digital audio interface receiver
C23
AOSDATA0
O
Digital audio data output to the power amp
C25
NS_XTALO
I
System clock signal input terminal (27 MHz)
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