Sony ExwaveHAD SSC-DC50A, Service Manual

Page: 43 / 64

6-5 SSC-DC50A/54A (UC)
SSC-DC50AP/54AP/58AP (CE)
IC
37
38
39
40
41
42
43
44
45
46
47
48
GND
V
DD
GND
24
23
22
21
20
19
18
17
16
15
14
13
GND
V
L
V
H
36 35 34 33 32 31 30 29 28 27 26 25
NC AV
DD
3
GND AV
DD
2
AV
DD
1
1 2 3 4 5 6 7 8 9
10 11 12
V
DD
GND GND
V
DD
1
34
23
24
19
18
17
36
37
DCIN
CKI
HD
VD
SCK
SDAT
SEN
TEST1
TEST2
DCOUT
MCK
PBLK
CLPDM
ID
WEN
XSHP
XSHD
XRS
ADCK
RG
H1
H2
V1
V2
V3
V4
SUB
CPP1
CPP2
CPP3
48
26
16
15
21
25
11
10
12
13
7
5
4
37
38
40
41
43
47
46
45
29
OSCI
31
RST
OSCO
32
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
I
—
—
O
O
—
O
—
—
O
O
O
O
—
O
O
I
I
I
—
O
—
I
I
DCIN
NC
AV
DD
3
H2
H1
GND
RG
AV
DD
2
AV
DD
1
XSHD
XSHP
XRS
ADCK
GND
LLPDM
PBLK
SEN
SDAT
SCK
V
DD
ID
GND
HD
VD
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
O
O
I
—
I
—
I
O
—
I
—
I
O
O
—
O
O
—
O
—
O
O
O
O
WEN
MCK
TEST2
V
DD
RST
GND
OSCI
OSCO
GND
CKI
V
DD
TEST1
V1
V2
GND
V3
V4
VL
SUB
VH
CPP3
CPP2
CPP1
DCOUT
PIN
NO.
I/O SIGNAL
PIN
NO.
I/O SIGNAL
C-MOS TIMING CONTROLLER WITH CCD DRIVERS
—TOP VIEW—
INPUT
CKI
DCIN
HD
OSCI
RST
SCK
SDAT
SEN
TEST1, TEST2
VD
OUTPUT
ADCK
CLPDM
CPP1 - CPP3
DCOUT
H1, H2
ID
MCK
OSCO
PBLK
RG
SUB
V1 - V4
WEN
XRS
XSHD
XSHP
; CLOCK
; OPERATIONAL AMPLIFIER INPUT FOR GENERATING
THE SUB CLAMP VOLTAGE
; HORIZONTAL SYNC SIGNAL
; OSCILLATOR
; RESET
; SERIAL COMMUNICATION CLOCK
; SERIAL COMMUNICATION DATA
; SERIAL COMMUNICATION STROBE
; TEST
; VERTICAL SYNC SIGNAL
; A/D CONVERTER CLOCK
; CLAMP PLUSE FOR CCD DUMMY SIGNAL
; CHARGE PUMP CAPACITORS
; OPERATIONAL AMPLIFIER OUTPUT FOR GENERATING
THE SUB CLAMP VOLTAGE
; CCD HORIZONTAL REGISTER DRIVE PULSES
; LINE IDENTIFICATION SIGNAL
; MODULATION CLOCK (1/2 CKI)
; OSCILLATOR
; BLANKING CLEANING PULSE
; CCD RESET GATE DRIVE PULSE
; CCD ELECTRON-CHARGE DRAIN PULSE
; CCD VERTICAL REGISTER DRIVE PULSES
; WRITE ENABLE SIGNAL
(ONLY IN LOW-SPEED SHUTTER OPERATION)
; A/D CONVERTER SAMPLE AND HOLD PULSE
; SAMPLE AND HOLD PULSE FOR DATA
; SAMPLE AND HOLD PULSE FOR PRECHARGING
DRIVER
XSHP
XSHD
XRS
ADCK
11
10
12
13
XSHP
XSHD
XRS
ADCK
RG DRIVER RG
7
H DRIVER
H1
H2
5
4
37
38
40
41
V DRIVER
V1
V2
V3
V4
SUB DRIVER
43
SUB
47
46
45
CHARGE
PUMP
CPP1
CPP2
CPP3
AMP
48
DCOUT DCIN
RST
TEST1
TEST2
1
29
36
27
RESET
19
17
18
MODE SET
LATCH
SCK
SEN
SDAT
16
15
21
25
PBLK
CLPDM
ID
WEN
VH
VL
44
42
32
31
OSCO
OSCI
1/2
34
CKI
26
MCK
TIMING GENERATOR
23 24
HD VD
CXD2480R-T4 (SONY)
AO1 - AO12
CK
DI
DO
LD
: 8-BIT D/A OUTPUTS
: CLOCK INPUT
: SERIAL DATA INPUT
: DATA OUTPUT
: DATA LOAD CONTROL INPUT (H : LOAD)
17
16
D1
AO1
AO2
AO3
AO4
AO5
AO6
AO7
AO8
AO9
AO10
AO11
AO12
DO
18
19
2
3
4
5
6
7
8
9
12
13
14
AO3
OUT
AO4
OUT
AO5
OUT
AO6
OUT
AO7
OUT
AO8
OUT
AO9
OUT
AO10
OUT
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
AO2
OUT
AO1
OUT
DI
IN
CK
IN
LD
IN
DO
OUT
AO12
OUT
AO11
OUT
GND
V
CC
V
DD
GND
15
LD
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
17
DI
16
CK
15
LD
ADDRESS
DECODER
12-BIT
SHIFT REGISTER
8-BIT
LATCH
8-BIT
R-2R
D/A CONV
+
_
AO12
13
8-BIT
LATCH
8-BIT
R-2R
D/A CONV
+
_
AO1
18
8 8 8
8 8
12
DO
14
C-MOS 8-BIT D/A CONVERTER
—TOP VIEW—
MB88346BPFV (FUJITSU)FLAT PACKAGE(SMALL)
MB88346BPFV-EF