Sony Esprit TAV-L1, Service Manual

Page: 133 / 210

133
TAV-L1
MAIN BOARD IC505 CXD9862R (DSP)
Pin No. Pin Name I/O Description
1
VSS
-
Ground terminal
2 XRST I Reset signal input from the main system controller "L": reset
3
EXTIN
I
Master clock signal input terminal Not used
4
LRCKI3
I
L/R sampling clock signal input terminal Not used
5 VDDI - Power supply terminal (+1.8V)
6
BCKI3
I
Bit clock signal input terminal Not used
7
PLOCK
O
PLL lock signal output terminal Not used
8
VSS
-
Ground terminal
9
MCLK1
I
System clock input terminal (13.9 MHz)
10
VDDI
-
Power supply terminal (+1.8V)
11
VSS
-
Ground terminal
12 MCLK2 O System clock output terminal (13.9 MHz)
13
MS
I
Master/slave setting terminal "L": internal clock, "H": external clock Fixed at "L" in this set
14
SCKOUT
O
Master clock signal output to the stream processor
15 LRCKI1 I L/R sampling clock signal input from the digital audio interface receiver
16
VDDE
-
Power supply terminal (+3.3V)
17
BCKI1
I
Bit clock signal input from the digital audio interface receiver
18 SDI1 I Audio serial data input from the digital audio interface receiver
19
LRCKO
O
L/R sampling clock signal output to the stream processor
20
BCKO
O
Bit clock signal output to the stream processor
21 VSS - Ground terminal
22
KFSIO
I
Audio clock signal input from the servo DSP or digital audio interface receiver
23
SDO1
O
Audio serial data output to the stream processor
24 SDO2 O Audio serial data output terminal Not used
25
SDO3
O
Audio serial data output to the stream processor
26
SDO4
O
Audio serial data output terminal Not used
27 SPDIF O SPDIF signal output terminal Not used
28
LRCKI2
I
L/R sampling clock signal input from the servo DSP or digital audio interface receiver
29
BCKI2
I
Bit clock signal input from the servo DSP or digital audio interface receiver
30
SDI2
I
Audio serial data input from the servo DSP or A/D converter
31
VSS
-
Ground terminal
32
HACN
O
Acknowledge signal output to the main system controllerr "L" active
33
HDIN
I
Serial data input from the main system controller
34 HCLK I Serial data transfer clock signal input from the main system controller
35
HDOUT
O
Serial data output to the main system controller
36
HCS
I
Chip enable input from the main system controller "L" active
37 GP12 I Write signal input from the main system controller
38
GP13
O
SD-RAM chip enable output terminal Not used
39
GP14
O
Row address strobe signal output terminal Not used
40 VDDI - Power supply terminal (+1.8V)
41
VSS
-
Ground terminal
42
GP15
O
Column address strobe signal output terminal Not used
43 OE0 O Output terminal of data input/output mask Not used
44
CS0
O
Chip select signal output to the S-RAM
45
WE0
O
Write enable signal output to the S-RAM
46 VDDE - Power supply terminal (+3.3V)