129
TAV-L1
Pin No.
Pin Name
I/O
Description
51
MAMUTE
O
Muting control signal output terminal Not used
52
DVDD18
-
Power supply terminal (+1.8V)
53 to 61
IOA2 to IOA8,
IOA18, IOA19
O
Address signal output to the flash ROM
62
DVSS
-
Ground terminal
63
APLLCAP
-
Connection terminal for an external capacitor
64
APLLVSS
-
Ground terminal
65
VDD3
-
Power supply terminal (+3.3V)
66
IOWR
O
Write enable signal output to the flash ROM
67 to 72
IOA16 to IOA11
O
Address signal output to the flash ROM
73
DVDD3
-
Power supply terminal (+3.3V)
74 to 76
IOA10, IOA9,
IOA20
O
Address signal output to the flash ROM
77
IOCS
O
Chip select signal output to the flash ROM
78
IOA1
O
Address signal output to the flash ROM
79
IOOE
O
Output enable signal output to the flash ROM
80
DVDD3
-
Power supply terminal (+3.3V)
81 to 84
AD0 to AD3
I/O
Data/address signal input/output terminal with the flash ROM
85
DVSS
-
Ground terminal
86 to 88
AD4 to AD6
I/O
Data/address signal input/output terminal with the flash ROM
89
IOA21
O
Address signal output to the flash ROM
90
ALE
O
Address latch enable signal output terminal Not used
91
AD7
I/O
Data/address signal input/output terminal with the flash ROM
92, 93
IOA17, IOA0
O
Address signal output to the flash ROM
94
DVSS
-
Ground terminal
95
UWR
O
Write enable signal output terminal Not used
96
URD
O
Data read enable signal output terminal Not used
97
DVDD18
-
Power supply terminal (+1.8V)
98
IFSDO
O
Serial data output to the main system controller
99
IFCK
O
Serial data transfer clock signal output to the main system controller
100
XIFCS
O
Chip select signal output to the main system controller
101
IFSDI
I
Serial data input from the main system controller
102
SCL
O
Serial data transfer clock signal output to the EEPROM
103
SDA
I/O
Two-way data bus with the EEPROM
104
TRG-SW
I
Trigger detection switch input terminal
105
IFBSY
I
Busy signal input from the main system controller
106
RXD
I
Receive data input terminal for UART communication when data writing to flash memory
107
TXD
O
Transmit data output terminal for UART communication when data writing to flash memory
108
DVDD3
-
Power supply terminal (+3.3V)
109
ICE
I
ICE mode enable signal input terminal Not used
110
PRST
I
Reset signal input from the main system controller "L": reset
111
IR
I
IR control signal input terminal Not used
112
INT0
O
Interrupt request signal output terminal Not used
113
DQM0
O
Data mask signal output to the SD-RAM
114
MREQ
O
Muting request signal output to terminal Not used
115
RD7
I/O
Two-way data bus with the SD-RAM
116
DVSS
-
Ground terminal
117, 118
RD6, RD5
I/O
Two-way data bus with the SD-RAM
Summary of Contents for Esprit TAV-L1
Page 10: ...10 TAV L1 MAIN board MAIN BOARD SERVICE POSITION ...
Page 46: ...46 TAV L1 MEMO ...
Page 209: ...209 TAV L1 MEMO ...
