52
DVP-NW50
Pin No.
Pin Name
I/O
Description
146
EGPIO05
O
CCLK signal output to DAR
147
EGPIO04
O
CSN signal output to DAR
148
EGPIO03
O
LCD RESET signal output
149
GND_RING
—
Ground terminal
150
VDD_RING
—
Power 3.3V
151
EGPIO02
O
LCD RS signal output
152
EGPIO01
O
LCD CLK signal output
153
EGPIO00
O
LCD DATA signal output
154
ARSTN
I
Reset signal input
155
TRSTN
I
JTAG I PD JTAG reset
156
ASDI
I
Primary input
157
USBM2
I/O
USB negative signals (not used)
158
USBP2
I/O
USB positive signals (not used)
159
WAITN
I
SRAM Wait in signal (not used)
160
EGPIO15
I
Key 0 signal input
161
GND_RING
—
Ground terminal
162
VDD_RING
—
Power 3.3V
163
EGPIO14
O
PWM1 output
164
EGPIO13
O
Key scan signal output
165
EGPIO12
I
Tuner SDA signal input
166
GND_CORE
—
Ground terminal
167
VDD_CORE
—
Power 1.8V
168
FGPIO3
I
Key 2 signal input
169
FGPIO2
I
Key 1 signal input
170
FGPIO1
I
DVDCE signal input
171
GND_RING
—
Ground terminal
172
VDD_RING
—
Power 3.3V
173
CLD
O
Collision detect
174
CRS
I
Carrier sense
175
TXERR
O
Transmit error signal output
176
TXEN
O
Transmit enable output
177
MIITXD0
O
Transmit data output
178
MIITXD1
O
Transmit data output
179
MIITXD2
O
Transmit data output
180
MIITXD3
O
Transmit data output
181
TXCLK
I
Transmit clock in
182
RXERR
I
PD receive data error in
183
RXDVAL
I
PD receive data valid in
184
MIIRXD0
I
Receive data in
185
MIIRXD1
I
Receive data in
186
MIIRXD2
I
Receive data in
187
GND_RING
—
Ground terminal
188
VDD_RING
—
Power 3.3V
189
MIIRXD3
I
Receive data in
190
RXCLK
I
Receive clock in
191
MDIO
O
Management data out
192
MDC
O
Management data clock out
193
RDN
O
Flash memory read / OE strobe out
194
WRN
O
Flash memory write strobe out