50
DVP-NW50
Pin No.
Pin Name
I/O
Description
48
AD0
O
Shared address bus out
49
VDD_RING
—
Power 3.3V
50
GND_RING
—
Ground terminal
51
NC
—
Not used
52
NC
—
Not used
53
VDD_RING
—
Power 3.3V
54
GND_RING
—
Ground terminal
55
AD15
O
Shared address bus out
56
DA7
I/O
Shared data bus in/out
57
VDD_CORE
—
Power 1.8V
58
GND_RING
—
Ground terminal
59
AD14
O
Shared address bus out
60
DA6
I/O
Shared data bus in/out
61
AD13
O
Shared address bus out
62
DA5
I/O
Shared data bus in/out
63
AD12
O
Shared address bus out
64
DA4
I/O
Shared data bus in/out
65
AD11
O
Shared address bus out
66
VDD_RING
—
Power 3.3V
67
GND_RING
—
Ground terminal
68
DA3
I/O
Shared data bus in/out
69
AD10
O
Shared address bus out
70
DA2
I/O
Shared data bus in/out
71
AD9
O
Shared address bus out
72
DA1
I/O
Shared data bus in/out
73
AD8
O
Shared address bus out
74
DA0
I/O
Shared data bus in/out
75
DSRN
O
Data set ready/data carrier detect (not used)
76
DTRN
O
Data terminal ready out
77
TCK
I
JTAG clock in
78
TDI
I
JTAG data in
79
TDO
O
JTAG data out
80
TMS
I
JTAG test mode select
81
VDD_RING
—
Power 3.3V
82
GND_RING
—
Ground terminal
83
BOOT1
I
Boot mode select in (not used)
84
BOOT0
I
Boot mode select in (not used)
85
GND_RING
—
Ground terminal
86
NC
—
Not used
87
EECLK
O
Two-wire interface clock output
88
EEDAT
O
Two-wire interface data output
89
ASYNC
I
Frame clock LRCK input
90
VDD_CORE
—
Power 1.8V
91
GND_CORE
—
Ground terminal
92
ASDO
O
Transmit data output
93
SCLK1
I/O
SPI bit clock (not used)
94
SFRM1
I/O
SPI frame (not used)
95
SSPRX1
I/O
SPI input (not used)
96
SSPTX1
I/O
SPI output (not used)