DSX-MS60
28
Pin No.
Pin Name
I/O
Description
58
BCK
I
Bit clock signal input from the USB controller
59
LRCK
I
L/R sampling clock signal (44.1 kHz) input terminal for audio data input
60
ZDET
O
Zero detection signal output terminal
61
VDD3
-
Power supply terminal (+3.3V)
62, 63
BUS0, BUS1
I/O
Bus data input/output with the USB controller
64
BUS2 (SO)
O
Serial data output to the USB controller
65
BUS3 (SI)
I
Serial data input from the USB controller
66
BUCK (CLK)
I
Bus clock signal input from the USB controller
67
/CCE
I
Chip enable signal input from the USB controller
68
MS
I
I/F mode selection signal input terminal Fixed at “H” in this set
69
/RST
I
Reset signal input from the USB controller
70
TEST
I
Setting terminal for test mode Normally
fi
xed at “L”
71
VDD1-2
-
Power supply terminal (+1.5V)
72
VSS
-
Ground terminal
73
/SRAMSTB
I
Strobe signal input from the USB controller “L”: standby mode
74
VDDM1
-
Power supply terminal (+1.5V)
75
PDO
O
Phase error margin signal between EFM signal and PLCK signal output terminal Not used
76
TMAX
O
TMAX detection result output terminal Not used
77
LPFN
I
Inverted signal input from the operation ampli
fi
er for PLL loop
fi
lter Not used
78
LPFO
O
Signal output from the operation ampli
fi
er for PLL loop
fi
lter Not used
79
PVREF
I
Reference voltage (+1.65V) input terminal Not used
80
VCOF
O
Terminal for VCO
fi
lter Not used
