Sony DPP-MS300 Marketing, Service Manual

Page: 65 / 88

5-68
Pin No. Pin Name I/O Description
57 P AS O
Address strobe signal output to the memory stick/PC card micro computer (IC1502), memory
stick controller (IC1503) and static RAM (IC1504)
58 P A17 O
Address signal output to the memory stick/PC card micro computer (IC1502), memory stick
controller (IC1503) and static RAM (IC1504)
59 VCC —
Power supply terminal (+5V)
60 P CLK O
Clock signal output to the memory stick/PC card micro computer (IC1502)
61 EXTCLK1 O
System clock (10 MHz) signal output to the memory stick/PC card micro computer (IC1502) and
memory stick controller (IC1503)
62 GND —
Ground terminal
63 to 68
P A16,
P A10 to P A6
O
Address signal output to the memory stick/PC card micro computer (IC1502), memory stick
controller (IC1503) and static RAM (IC1504)
69 GND —
Ground terminal
70 to 75 P A5 to P A0 O
Address signal output to the memory stick/PC card micro computer (IC1502), memory stick
controller (IC1503) and static RAM (IC1504)
76 VCC —
Power supply terminal (+5V)
77 to 80 P D7 to P D4 I/O
Two-way data bus with the memory stick/PC card micro computer (IC1502), memory stick
controller (IC1503) and static RAM (IC1504)
81 GND —
Ground terminal
82 to 85 P D3 to P D0 I/O
Two-way data bus with the memory stick/PC card micro computer (IC1502), memory stick
controller (IC1503) and static RAM (IC1504)
86 P IREQ4 O
Interrupt request signal output to the memory stick/PC card micro computer (IC1502)
87 VCC —
Power supply terminal (+5V)
88 GND —
Ground terminal
89 to 92 H D3 to H D6 I/O
Two-way data bus with the A/D, D/A converter (IC407), system controller (IC503), mechanism
controller (IC505), ROM (IC506), D-RAM (IC509) and PC card slot
Data input from the centronics parallel port
93 to 95 H D11 to H D13 I/O
In/out terminal for the data signal Not used (fixed at “L”)
96 GND —
Ground terminal
97 H D14 I/O
In/out terminal for the data signal Not used (fixed at “L”)
98 H D7 I/O
Two-way data bus with the A/D, D/A converter (IC407), system controller (IC503), mechanism
controller (IC505), ROM (IC506), D-RAM (IC509) and PC card slot
Data input from the centronics parallel port
99 H CE1 I Chip enable signal input from the system controller (IC503)
100 H A10 I Address signal input from the system controller (IC503) and PC card slot
101 H OE I Output enable signal input from the system controller (IC503)
102 H D15 I/O In/out terminal for the data signal Not used (fixed at “L”)
103 H CE2 I Chip enable signal input terminal Not used (fixed “H”)
104 H IORD I Data read enable signal input from the system controller (IC503)
105 H IOWR I Data write enable signal input from the system controller (IC503)
106 VCC — Power supply terminal (+5V)
107 to 110 H A9 to H A6 I Address signal input from the system controller (IC503) and PC card slot
111 GND — Ground terminal
112 H WE I Data write enable signal input from the system controller (IC503)
113 H IREQ O Busy signal output to the system controller (IC503)
114 NC — Not used (open)
115 TA1 I Input terminal for the test (normally: fixed at “L”)
116 H RESET I Reset signal input from the system controller (IC503)
117 H WAIT O Wait signal output to the system controller (IC503) “L” active
118 to 120 H A5 to H A3 I Address signal input from the system controller (IC503) and PC card slot