Sony D-VE45, Service Manual

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13
D-VE45
• IC701 CL680T-P-D1 (AUDIO/VIDEO MPEG DECODER)
Pin No. Pin Name I/O Pin Description
1 NC — Not used. (Open)
2 VSS — Ground
3 CD_BCK I CD decode bit clock signal (2.8224 MHz) input from the CXD3028R (IC601).
4 CD_DATA I CD decode data input from the CXD3028R (IC601).
5 CD_LRCK I CD decode L/R sampling clock signal (44.1 kHz) input from the CXD3028R (IC601).
6 CD_C2PO I CD decode C2 error data input from the CXD3028R (IC601).
7 – 9 NC — Not used. (Open)
10 – 15 MD0 – 5 I/O Two-way data bus with the program ROM (IC704) and DRAM (IC703).
16 VSS — Ground
17 MD6 I/O Two-way data bus with the program ROM (IC704) and DRAM (IC703).
18 VDD3 — Power supply pin (+3.3 V)
19 MD7 I/O Two-way data bus with the program ROM (IC704) and DRAM (IC703).
20 VSS — Ground
21 MD8 I/O Two-way data bus with the program ROM (IC704) and DRAM (IC703).
22 VDD3 — Power supply pin (+3.3 V)
23 – 28 MD9 – 14 I/O Two-way data bus with the program ROM (IC704) and DRAM (IC703).
29 MD15 I/O Two-way data bus with the program ROM (IC704).
30 – 36 NC — Not used. (Open)
37 MCE O Chip enable signal output to the program ROM (IC704).
38 MWE O Write enable signal output to the DRAM (IC703).
39 VSS — Ground
40 CAS O Column address strobe signal output to the DRAM (IC703).
41 VDD3 — Power supply pin (+3.3 V)
42 RAS0 O Row address strobe signal output to the DRAM (IC703).
43 RAS1 O Row address strobe signal output (Not used in this set)
44, 45 MA10, 9 O Address signal output to the program ROM (IC704).
46 MA8 O Address signal output to the program ROM (IC704) and DRAM (IC703).
47 VSS — Ground
48 MA7 O Address signal output to the program ROM (IC704) and DRAM (IC703).
49 VDD3 — Power supply pin (+3.3 V)
50 – 52 MA6 – 4 O Address signal output to the program ROM (IC704) and DRAM (IC703).
53 VSS — Ground
54 MA3 O Address signal output to the program ROM (IC704) and DRAM (IC703).
55 VDD3 — Power supply pin (+3.3 V)
56 – 58 MA2 – 0 O Address signal output to the program ROM (IC704) and DRAM (IC703).
59 PGIO7 I/O Not used. (Open)
60 RESET I Reset signal input from TMP87CM41U (IC803). (L: Reset)
61 VDDMAX_IN I Fix the maximum input voltage each input pin and input/output pin.
62 – 64 NC — Not used. (Open)
65 AGND_DAC — Ground (for D/A converter)
66 AVDD_DAC — Power supply pin (+3.3 V) (for D/A converter)
67 COMPOS_OUT O Composite video signal output
68 AGND_DAC — Ground (for D/A converter)
69 Y-OUT O Luminance video signal output (Not used in this set)
70 AVDD_DAC — Power supply pin (+3.3 V) (for D/A converter)
71 AGND_DAC — Ground (for D/A converter)
72 RREF I Fix the video signal output level control.
73 VREF O Reference voltage (+1.235 V) output
74 AVDD_DAC — Power supply pin (+3.3 V) (for D/A converter)
75 C-OUT O Chrominance video signal output (Not used in this set)
76 AGND_DAC — Ground (for D/A converter)
77 CLK_SEL (0) I Clock select 0 input (Fixed at “H” in this set)
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