CXD5602 User Manual
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3.9.5
Power Supply Control
The SCU module belongs to a power domain called PWD_SCU.
Within the PWD_SCU, there are power supply control module regions (listed below) as separate power domains.
Refer to the PMU Chapter (3.4) for details on the ON/OFF control registers of these power domains.
Table SCU (Sensor Control Unit)-88 Power Supply Control Registers
Power Supply Control Target
Control Register Name
LPADC
ANA_PW_CTL
HPADC
ANA_PW_CTL
FIFO SRAM (8KByte)
SCU_RAMMODE_SEL
FIFO SRAM (32KByte)
SCU_RAMMODE_SEL
Internal Sequencer SRAM (Instruction, Data)
SCU_RAMMODE_SEL
3.9.6
Interrupt
3.9.6.1
Overview
The SCU has four lines of interrupts, which connect to the SYSCPU and DSP.
For details, refer to the Chapter on Interrupt (3.3).
The following shows the relation with the interrupt number.
Table SCU (Sensor Control Unit)-89 Interrupt Number
SCU Interrupt Name
Description
INT0
SPI interrupt
INT1
I2C0 interrupt
INT2
I2C1 interrupt
INT3
Event Interrupt
3.9.6.2
Interrupt Details
The interrupts that occur within the SCU are connected to the CPU in the SYSIOP and the CPU in the GNSS;
(hereinafter referred as “upper CPUs” in the Chapter on SCU), and also notified to the internal sequencer of the
SCU.
The interrupts to the upper CPUs are integrated into four interrupts at the INT_SEL module, and then output.
The interrupts from the SPI, I2C0, and I2C1 are output separately from the other interrupts.
Other interrupts such as LPADC, HPADC, PWM, and FIFO are ORed within the INT_SEL and combined into
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