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27
CX-LFA500
LEVEL S
HIFT
INT
E
RF
ACE
INT
E
RF
ACE
INT
E
RF
ACE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
20
21
22
23
24
25
26
27
28
19
18
17
16
15
F
R
R
F
F
R
R
F
R
R
F
F
M
U
T
E
TH
E
RM
AL
S
H
U
T
DO
WN
V
R
E
F
OU
T
V
R
E
FIN
P
O
W
VCC
C
H
1
FIN
C
H
1
RIN
C
H
2
FIN
C
H
2
RIN
C
H
2OU
TR
C
H
2OU
TF
C
H
1OU
TR
C
H
1OU
TF
CA
P
A
IN
1
CA
P
A
IN
2
G
N
D
PRF
VCC
M
U
T
E
P
O
W
VCC
C
H
4S
IN
'
C
H
4S
IN
C
H
4B
IN
C
H
3
FIN
C
H
3
RIN
C
H
3OU
TR
C
H
3OU
TF
C
H
4OU
TR
C
H
4OU
TF
CA
P
A
IN
3
G
N
D
• IC Block Diagrams
IC101
CXD3017Q
IC102
BA5974FP-E2
T
E
RF
DC
CE
I
GE
N
AVSS0
AD
I
O
AVDD0
CL
T
V
FI
LO
AVSS3
VSS
AVDD3
DOU
T
VDD
P
CO
FI
L
I
ASYO
ASY
I
RF
AC
B
I
AS
SS
TP
D
F
C
T
MIRR
M
D
P
LOC
K
F
O
K
S
F
D
R
VSS
T
ES
T
FR
D
R
F
E
VC
COU
T
SE
X
T
SL
T
ES1
S
R
D
R
TF
D
R
FF
D
R
TR
D
R
2
1
70
71
68
69
66
67
64
65
62
61
63
73
74
72
75
76
77
78
79
80
4
X
R
S
T
3
SQC
K
SQSO
5
9
8
7
6
56
60
53
54
55
59
57
58
51
52
48
49
50
47
44
45
46
43
41
42
XLA
T
CLO
K
SE
N
S
SYS
M
DA
T
A
XUG
F
X
P
C
K
G
F
S
C2
P
O
WF
C
K
10 11 12 13 14 15 16 17 18 19 20
21
22
23
24
25
26
32
33
30
31
36
37
34
35
39
40
38
28
27
29
S
P
OA
A
T
S
K
SCL
K
VDD
SCO
R
S
P
OB
XLO
N
X
T
A
I
XVDD
E
MPH
AVDD1
AOU
T
1
A
IN
1
X
T
AO
XVSS
A
IN
2
AOU
T
2
AVDD2
RM
U
T
LOU
T
2
LOU
T
1
BC
K
L
R
C
K
P
C
M
D
L
M
U
T
AVSS1
AVSS2
C
P
U
INT
E
RF
ACE
SE
R
VO AU
T
O
SEQUE
N
CE
R
SE
RI
AL
IN
INT
E
RF
ACE
OVE
R
SA
MP
L
IN
G
D
I
G
IT
AL
FI
L
T
E
R
3rd O
R
DE
R
N
O
I
SE S
H
A
P
E
R
PWM
PWM
E
FM
DE
M
ODULA
T
O
R
TIMIN
G
LOG
I
C
D
I
G
IT
AL
OU
T
D/A
INT
E
RF
ACE
D
I
G
IT
AL
P
LL
ASY
MM
E
TR
Y
CO
RR
EC
T
O
R
CLOC
K
GE
N
E
R
A
T
O
R
MIRR,
D
F
C
T,
F
O
K
DE
T
EC
T
O
R
D
I
G
IT
AL
CLV
SUBCODE
PR
OCESSO
R
SE
R
VO
INT
E
RF
ACE
SE
R
VO DS
P
F
OCUS
SE
R
VO
TR
AC
KIN
G
SE
R
VO
SLED
SE
R
VO
PWM
GE
N
E
R
A
T
O
R
F
OCUS
PWM
GE
N
E
R
A
T
O
R
TR
AC
KIN
G
PWM
GE
N
E
R
A
T
O
R
SLED
PWM
GE
N
E
R
A
T
O
R
16
K
R
A
M
E
RR
O
R
CO
RR
EC
T
O
R
INT
E
RN
AL BUS
A/D
CO
N
VE
RT
E
R
O
P
E
R
A
TI
O
N
AL
A
MP
L
IFI
E
R
A
N
ALOG S
WIT
C
H
– CD Board –
Summary of Contents for CX-LFA500
Page 12: ...12 CX LFA500 MEMO ...