4-12
CA-755/755P
IC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
FB
(FEEDBACK) IN
A
IN
B
IN
Q
B OUT
Q
A OUT
Q
C OUT
C
IN
V
DD
(+3 V to +12 V)
RD
(RESET DIRECT) IN
CK
(CLOCK) IN
Q
E OUT
E
IN
Q
D OUT
PE
(PRESET ENABLE) IN
D
IN
GND
DIVIDE
BY
10
9
8
7
6
5
4
3
2
14
1
10
PE
11
13
5
4
6
Q
A
Q
B
Q
C
Q
D
Q
E
9
D
15
R
D
FB
2
A
3
B
7
C
12
E
C-MOS PRESETTABLE DIVIDE-BY-N COUNTER
— TOP VIEW —
CONNECT TO FB
INPUT
Q
E
Q
D,
Q
E
Q
D
Q
C,
Q
D
Q
C
Q
B,
Q
C
Q
B
Q
A,
Q
B
Q
A
5 COUNTS HIGH, 5 COUNTS LOW
5 COUNTS HIGH, 4 COUNTS LOW
4 COUNTS HIGH, 4 COUNTS LOW
4 COUNTS HIGH, 3 COUNTS LOW
3 COUNTS HIGH, 3 COUNTS LOW
3 COUNTS HIGH, 2 COUNTS LOW
2 COUNTS HIGH, 2 COUNTS LOW
2 COUNTS HIGH, 1 COUNTS LOW
1 COUNTS HIGH, 1 COUNTS LOW
RESULTS FROM EACH Q OUTPUT
VIA
DIRECT
AND GATE
DIRECT
AND GATE
DIRECT
AND GATE
DIRECT
AND GATE
DIRECT
C-MOS 14-STAG RIPPLE-CARRY BINARY COUNTER/DRIVER
—TOP VIEW—
0
1
2
3
4
16380
16381
16382
16383
Q13
0
0
0
0
0
1
1
1
1
Q12
0
0
0
0
0
1
1
1
1
0000
0001
0002
0003
0004
4FFC
4FFD
4FFE
4FFF
*
V
DD
OUT
OUT
OUT
OUT
OUT
OUT
OUT
COUNT
BINARY OUTPUTS
1
2
3
4
5
6
7
Q11
Q12
Q13
Q5
Q4
Q6
Q3
Q10
Q9
Q7
Q8
Q0
R
D
R
D
CK
8
10
11
12
13
14
15
16
9
0 ; LOW LEVEL
1 ; HIGH LEVEL
CK
Q0
Q3
11
10
H
H
K R
D
R
D
R
D
R
D
R
D
J
Q
Q
Q
Q
Q
Q
R
D
IN HEXADECIMAL
IN DECIMAL
GND
OUT
10
11
9
7
5
4
6
13
12
14
15
1
2
3
Q0
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
Q12
Q13
OUT
OUT
OUT
IN
IN
OUT
Q11
0
0
0
0
0
1
1
1
1
Q10
0
0
0
0
0
1
1
1
1
Q9
0
0
0
0
0
1
1
1
1
Q8
0
0
0
0
0
1
1
1
1
Q7
0
0
0
0
0
1
1
1
1
Q6
0
0
0
0
0
1
1
1
1
Q5
0
0
0
0
0
1
1
1
1
Q4
0
0
0
0
0
1
1
1
1
Q3
0
0
0
0
0
1
1
1
1
Q0
0
1
0
1
0
0
1
0
1
TYPE
HC4020
14020, 4020, 84020
*
+2 to +6V
+3 to +18V
V
DD
RD
1
0
ALL LOW
COUNT
Q13-Q0
•••
•••
•••
•••
•••
•••
•••
•••
•••
•••
•••
•••
•••
•••
9
H
H
K
J
H
H
K
J
H
H
K
J
H
H
K
J
H
H
K
J
7
Q12
Q13
2
3
-TOP VIEW-
C-MOS 2-INPUT NAND GATE
0
1
; LOW LEVEL
; HIGH LEVEL
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
DD
(+3 to +18V)
A
0
0
1
1
B
0
1
0
1
Y
1
1
1
0
GND
A
B
Y =
A
B
Y
Y = A • B = A + B
MC14011BF (MOTOROLA)FLAT PACKAGE
MC14011BFEL
MC14020BFEL (MOTOROLA)FLAT PACKAGE
MC14018BFEL (MOTOROLA)FLAT PACKAGE
C-MOS TRIPLE 2-CHANNEL ANALOG MULTIPLEXERS/DEMULTIPLEXERS
— TOP VIEW —
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
X1
IN/OUT
X0
IN/OUT
Y1
IN/OUT
YC
IN/OUT
Y0
IN/OUT
EN
IN
V
DD
(+3 V to +18 V)
XC
IN/OUT
ZC
IN/OUT
Z1
IN/OUT
Z0
IN/OUT
AZ
IN/OUT
AX
IN/OUT
AY
IN/OUT
GND
6
EN
V
EE
V
EE
* ; V
DD
–
V
EE
+
3 V
+
18 V
*
7
V
EE
1
X1
2
X0
10 AX
15
XC
OPEN
3
Y1
5
Y0
9
AY
4
YC
OPEN
13 Z1
12 Z0
11 AZ
14
ZC
OPEN
CONT. INPUTS
EN
0
0
1
0
1
X
;
;
;
LOW LEVEL
HIGH LEVEL
DON'T CARE
A (X, Y, Z)
0
1
X
0
1
OPEN
ON
CHANNEL
MC14053BF (MOTOROLA)FLAT PACKAGE
MC14053BFEL
1
2
3
4
5
6
7
8
PCP
(PHASE COMPARATOR) OUT
PC
1
(PHASE COMPARATOR) OUT
PC
B
(PHASE COMPARATOR) IN
VCO
(VOLTAGE CONTROLLED OSC) OUT
INH
(INHIBIT) IN
-TOP VIEW-
16
15
14
13
12
11
10
9
GND
Z
D
(ZENER) OUT
PC
A
(PHASE COMPARATOR) IN
PC
2
(PHASE COMPARATOR) OUT
SF
(SOURCE FOLLOWER) OUT
VCO
(VOLTAGE CONTROLLED OSC) IN
*
1
V
DD
2
13
1
4
6
7
10
15
PC1
PC2
PCP
VCO
OUT
C1A
C1B
SF
ZD
C-MOS PHASE LOCKED LOOP
14
3
9
11
12
5
PCA
PCB
VCO
IN
R1
R2
INH
C1
A
C1
B
R
2
R
1
SELF
BIAS
CIRCUIT
PHASE
COMPARATOR 1
PHASE
COMPARATOR 2
VCO
SOURCE
FOLLOWER
14
PCA
3
PCB
9
VCO
5
INH
GND
15
ZD
10
SF
7
C1B
6
C1A
12
R2
11
R1
4
VCO
1
PCP
13
PC2
2
PC1
TYPE
CD4046BE
HD14046BP
MC14046BCP
MC14046BF
TC4046BP
CD74HC4046AM
MC74HC4046AF
MC74HC4046AN
V
DD
+3 to +8V
+2 to +6V
*
1
MC14046BF (MOTOROLA)FLAT PACKAGE
Summary of Contents for CA-755
Page 4: ......
Page 10: ......
Page 92: ......
Page 98: ...5 6 CA 755 755P 5 6 RX 37 Block Diagram Block Diagram RX 37 RX 37 CA 755 CA 755P ...
Page 100: ......
Page 102: ......
Page 104: ......
Page 106: ......
Page 108: ......
Page 110: ......
Page 111: ...7 1 CA 755 755P 7 1 2 3 4 5 1 I J K L M N O P Section 7 Schematic Diagrams ...
Page 126: ...7 16 CA 755 755P 7 16 2 3 4 5 A B C D E F G H 1 ...
Page 130: ......
