
- 35 -
DD
CC
BB
P
EE
FF
Z
1
2
3
4
5
6
7
8
9
10
11
12
Q
R
S
T
U
V
W
X
Y
AA
0 . 1
C5026
10k
R5016
0 . 1
C5027
0 . 1
C5031
0 . 1
C5039
1608
16V
0 . 1
B
C5034
3.3V_MAIN
0 . 1
C5030
0 . 1
C5044
10k
R5017
10k
R5015
8765
4
3
2
1
IC5003
nCS
DATA
VCC
GND
ASDI
DCLK
VCC
VCC
1608
16V
0 . 1
B
C5022
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
134
135
136
137
138
139
140
141
142
143
144
IO/ASDO
IO/nCSO
IOLVDS15p/CRC_ERROR
IO/LVDS15n/CLKUSR
VCCIO1
GND
IO/VREFB1N0
IO/LVDS8p
IO/LVDS8n
TDO
TMS
TCK
TDI
DATA0
DCLK
nCE
CLK0/VDSCLK0p/input(3)
CLK1/VDSCLK0n/input(3)
GND
nCONFIG
CLK2/VDSCLK1p/input(3)
CLK3/VDSCLK1n/input(3)
VCCIO1
IO/LVDS7p
IO/LVDS7n
VCCINT
GND
IO/VREFB1N1
VCCIO1
IO
IO/PLL1_OUTp
IO/PLL1_OUTn
GND
GND_PLL1
VCCD_PLL1
GND_PLL1
VCCA_PLL1
GNDA_PLL1
GND
IO/LVDS77n/DEV_OE
IO/LVDS77p
OI/LVDS76p
IO/LVDS76n
IO/LVDS75p
IO/LVDS75n
VCCIO4
IO/LVDS74p
IO/LVDS23p
IO/LVDS19n
IO/LVDS19p
IO/LVDS18n
VCCIO2
IO/LVDS18p
GND
IO/LVDS17p
IO/LVDS17n/DEV CLRn
IO/LVDS16p
IO/LVDS16n
XX
L5007
3.3V_MAIN
100
C5046
1.2V_MAIN
100
C5045
0 . 1
C5021
1000p
C5025
1uH
L5008
10
C5018
FPGA_RESETQ
10
RB5016
SCL
SDA
R5022
100
R5023
100
CLKIN_2025
JL5017
JL5020
JL5021
JL5002
JL5003
5001
JL5011
JL5012
JL5013
JL5014
JL5015JL5016
JL5008
JL5004
R5012
XX
XX
R5018
JL5023
FPGA_CONF_DONE
JL5024
R5030
0
R5031
0
R5032
0
R5033
0
100
R5019
XX
L5010
XX
L5011
1
2
3
4
5
6
7
8
9
10
11
12
13
14
CN5001
GND
DCLK
nCONFIG
ASDI
CONF_DONE
GND
NC
VCC
VCC
NC
nCE
nCS
DATAOUT
GND
CHIP
0
JR5002
JR5000
0
JR5001
0
R5057
0
R5058
0
R5059
0
FPGA_CONFIG
CHIP
0
JR5007
0
JR5010
0
JR5011
3.3V_MAIN
0 . 1
C5056
0 . 1
C5057
0 . 1
C5058
0 . 1
C5059
TP5025
TP5026
TP5027
TP5028
TP5029
TP5030
TP5031
TP5032
TP5033
GND_1
GND_1
GND_1
DBO1
DBO0
DGO1
DGO0
DRO1
DRO0
DBO3
DBO2
DGO2
DRO3
DRO2
DEN_OUT
DEN_OUT
DVS_OUT
DVS_OUT
DHS_OUT
DBO9
DBO8
GND_1
GND_1
GND_1
PORT_A_A25_R5
PORT_A_A24_R4
PORT A A23 R3
PORT_A_A28_R8
PORT_A_A26_R6
PORT_A_A27_R7
PORT_A_A29_R9
GND_1
PCLKOUT
DGO3
GND_1
GND_1
DEN_OUT_AR
DRO8_AR
DVS_OUT_AR
DHS_OUT_AR
DBO7_AR
DBO6_AR
DGO8_AR
DRO9_AR
FPGA WINGMAN
GNDA_PLL1
TO IC5002
PLACE AS CLOSE AS POSSIBLE
Imax = 2A
Imax = 2A
Imax = 455mA
ADD CAPACITOR CLOSE VIAS PORT_A LINES (EMC)
6B/13
BC
BC.SE1A
~ BC Board Schematic Diagram [ Tuner, Audio/Video Processor, HDMI & PC Input ] Page 6B/13 ~
Summary of Contents for Bravia KDL-26T3000
Page 9: ... 8 SE1A RM ED009 SECTION 2 DISASSEMBLY 2 2 STAND REMOVAL 2 1 REAR COVER REMOVAL ...
Page 10: ... 9 SE1A RM ED009 2 3 COVER UNDER REMOVAL 2 4 AC INLET REMOVAL ...
Page 11: ... 10 SE1A RM ED009 2 5 LOUD SPEAKER REMOVAL 2 6 H1 BOARD REMOVAL ...
Page 12: ... 11 SE1A RM ED009 2 7 BC BOARD REMOVAL ...
Page 13: ... 12 SE1A RM ED009 2 8 U1 26 inches or U2 32 and 40 inches BOARD REMOVAL 2 9 H2 BOARD REMOVAL ...
Page 15: ... 14 SE1A RM ED009 2 12 VESA ARM and LCD PANEL REMOVAL 26 and 32 inches ...
Page 16: ... 15 SE1A RM ED009 2 13 VESA ARM and LCD PANEL REMOVAL 40 inches ...