Sony BKDS-PA3291, Maintenance Manual

Page: 92 / 140

6-14
BVS-A3232/V3232
IC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
DCDA
IN
D7
IN/OUT
D6
IN/OUT
D5
IN/OUT
D4
IN/OUT
D3
IN/OUT
D2
IN/OUT
D1
IN/OUT
D0
IN/OUT
WR
IN
RD
IN
C/D
IN
B/A
IN
PRO
OUT
PRI
IN
INTAK
IN
INT
OUT
CTSB
IN
DCDB
IN
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
GND
V
DD
(+5V)
CTSA
IN
R
X
DA
IN
XI1A/STR
X
CA
IN
XI2A/SYNCA
IN/OUT
TR
X
CA
IN/OUT
T
X
DA
OUT
RTSA
OUT
DRQR
X
A
OUT
RESET
IN
CK
IN
DRQT
X
A
IN/OUT
DTRA/DRQT
X
B
OUT
DTRB/DRQR
X
B
OUT
RTSB
OUT
T
X
DB
OUT
XI2B/SYNCB
IN/OUT
XI1B/STR
X
CB
IN
R
X
DB
IN
TR
X
CB
IN/OUT
39
40
1
38
22
19
20
23
31
12
11
13
14
32
17
16
R
X
DA
CTSA
DCDA
XI1A/STR
X
CA
R
X
DB
CTSB
DCDB
XI1B/STR
X
CB
ø
RD
WR
C/D
B/A
RESET
INTAK
PRI
35
37
36
34
25
24
21
26
9
8
7
6
5
4
3
2
33
29
27
28
18
15
T
X
DA
XI2A/SYNCA
TR
X
CA
RTSA
T
X
DB
XI2B/SYNCB
TR
X
CB
RTSB
D0
D1
D2
D3
D4
D5
D6
D7
DRQR
X
A
DRQT
X
A
DTRB/DRQR
X
B
DTRA/DRQT
X
B
INT
PRO
–TOP VIEW–
C-MOS ADVANCED MULTI-PROTOCOL SERIAL CONTROLLER
UPD72001C-11 (NEC) (CLOCK FREQUENCY:11MHz)
CLOCK/
STANDBY
CONTROL
DATA BUS
BUFFER
READ/
WRITE
CONTROL
DMA
CONTROL
INTERRUPT
CONTROL
31
CK
12
RD
11
WR
32
RESET
16
PRI
15
PRO
18
INT
17
INTAK
13
C/D
14
B/A
33
DRQR
X
A
29
DRQT
X
A
27
DTRB/DRQR
X
B
28
DTRA/DRQT
X
B
D7–D0
CHANNEL B
CHANNEL A
INTERNAL BUS
CONTROL
SIGNAL
CR0–CR5
CR10–CR15
CR8, CR9
SR8, SR9
BRG–H, L
BRG
T
X
R
X
CLOCK
CONTROL
DPLL
OSC
T
X
R
X
CONTROL
RECEIVER
TRANSMITTER
T
X
BUFFER
CR6,
CR7
R
X
SR0
BUFF 4–7
SR1–SR4
SR10, SR11
0–3
T
X
R
X
CLOCK
R
X
CLK
T
X
CLK
34
RTSA
36
TR
X
CA
37 1
DCDA
39
R
X
DA
35
T
X
DA
40
CTSA
38
XI1A/
STR
X
CA
XI2A/
SYNCA
SR12–SR15
RTSB
26
TR
X
CB
21
DCDB
20
CTSB
19
R
X
DB
22
T
X
DB
25
XI1B/
STR
X
CB
23
XI2B/
SYNCB
24
INPUTS
FUNCTION
CHANNEL A
CHANNEL B
CHANNEL A
CHANNEL B
CHANNEL A
CHANNEL B
CHANNEL A
CHANNEL B
HIGH-IMPEDANCE
INHIBIT
0
1
X
; LOW LEVEL
; HIGH LEVEL
; DON'T CARE
WRITE (T
X
D)
READ (R
X
D)
WRITE (CONTROL REGISTER)
READ (STATUS REGISTER)
WR
0
1
0
1
1
0
C/D
0
0
1
1
X
X
RD B/A
0
1
0
1
0
1
0
1
X
X
1
0
1
0
1
0
CK
WR
RD
B/A
C/D
D0–D7
INT
INTAK
PRI
DRQT
X
A
DRQR
X
A
PRO
; SYSTEM CLOCK INPUT
; WRITE ENABLE INPUT
; READ ENABLE INPUT
; CHANNEL B/A SELECT INPUT
; CONTROL/DATA SELECT INPUT
; DATA BUS INPUTS/OUTPUTS
; INTERRUPT OUTPUT
; INTERRUPT ACKNOWLEDGE INPUT
; PRIORITY INPUT
; DMA REQUEST T
X
A OUTPUT
; DMA REQUEST R
X
A OUTPUT
; PRIORITY OUTPUT
DTRA/DRQT
X
B
DTRB/DRQR
X
B
CTSA, CTSB
DCDA, DCDB
RTSA, RTSB
RESET
; DATA TERMINAL READY A/DMA REQUEST T
X
B OUTPUT
; DATA TERMINAL READY B/DMA REQUEST R
X
B OUTPUT
; CLEAR TO SEND A/B INPUT
; DATA CARRIER DETECT A/B INPUT
; REQUEST TO SEND A/B OUTPUT
; RESET INPUT