SONIX SN8P27142_2715 User Manual Download Page 83 | Manualshive

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SN8P2714X_2715

8-bit micro-controller build-in 12-bit ADC

SONiX TECHNOLOGY CO., LTD

Page 83

V1.4

9.5.2 INT0 (P0.0) INTERRUPT OPERATION

The INT0 is triggered by falling edge. When the INT0 trigger occurs, the P00IRQ will be set to “1” however the P00IEN
is enable or disable. If the P00IEN = 1, the trigger event will make the P00IRQ to be “1” and the system enter interrupt
vector. If the P00IEN = 0, the trigger event will make the P00IRQ to be “1” but the system will not enter interrupt vector.
Users need to care for the operation under multi-interrupt situation.

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Example: INT0 interrupt request setup.

B0BSET

FP00IEN

; Enable INT0 interrupt service

B0BCLR

FP00IRQ

;

Clear

INT0 interrupt request flag

B0BSET

FGIE

; Enable GIE

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Example: INT0 interrupt service routine.

ORG

8

; Interrupt vector

JMP

INT_SERVICE

INT_SERVICE:

B0XCH

A, ACCBUF

; B0XCH doesn’t change C, Z flag

B0MOV

A,

PFLAG

B0MOV

PFLAGBUF, A

; Save PFLAG register in a buffer

B0BTS1

FP00IRQ

; Check P00IRQ

JMP

EXIT_INT

; P00IRQ = 0, exit interrupt vector

B0BCLR

FP00IRQ

; Reset P00IRQ

.

.

; INT0 interrupt service routine

. .

EXIT_INT:

B0MOV

A,

PFLAGBUF

B0MOV

PFLAG, A

; Restore PFLAG register from buffer

B0XCH

A, ACCBUF

; Restore ACC value.

RETI

; Exit interrupt vector

9.5.3 INT1 (P0.1) INTERRUPT OPERATION

The INT1 is triggered by falling edge. When the INT1 trigger occurs, the P01IRQ will be set to “1” however the P01IEN
is enable or disable. If the P01IEN = 1, the trigger event will make the P01IRQ to be “1” and the system enter interrupt
vector. If the P01IEN = 0, the trigger event will make the P01IRQ to be “1” but the system will not enter interrupt vector.
Users need to care for the operation under multi-interrupt situation.

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Example: INT1 interrupt request setup.

B0BSET

FP01IEN

; Enable INT1 interrupt service

B0BCLR

FP01IRQ

;

Clear

INT1 interrupt request flag

B0BSET

FGIE

; Enable GIE

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Summary of Contents for SN8P27142_2715

Page 1: ...ntended or authorized for us as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the fa...

Page 2: ...ormula 4 Remove Note For 12 bit resolution the conversion time is 16 steps 5 Remove Note Please use RST_WDT macro to clear the watchdog timer successfully both in S8KD 2 ICE emulation and real chip 6...

Page 3: ...IAGRAMS 14 2 CODE OPTION TABLE 15 3 ADDRESS SPACES 16 3 1 PROGRAM MEMORY ROM 16 3 1 1 OVERVIEW 16 3 1 2 USER RESET VECTOR ADDRESS 0000H 17 3 1 3 INTERRUPT VECTOR ADDRESS 0008H 17 3 1 4 GENERAL PURPOSE...

Page 4: ...K 0 36 5 2 1 BYTES of SYSTEM REGISTER 36 5 2 2 BITS of SYSTEM REGISTER 37 6 RESET 39 6 1 OVERVIEW 39 6 2 POWER ON RESET 40 6 3 WATCHDOG RESET 40 6 4 BROWN OUT RESET 41 6 4 1 BROWN OUT DESCRIPTION 41 6...

Page 5: ...7 8 2 TIMER COUNTER 0 TC0 58 8 2 1 OVERVIEW 58 8 2 2 TC0M MODE REGISTER 59 8 2 3 TC0C COUNTING REGISTER 61 8 2 4 TC0R AUTO LOAD REGISTER 63 8 2 5 TC0 TIMER COUNTER OPERATION SEQUENCE 64 8 2 6 TC0 CLOC...

Page 6: ...0 3 PULL UP RESISTERS 91 10 4 I O PORT DATA REGISTER 94 11 8 CHANNEL ANALOG TO DIGITAL CONVERTER 96 11 1 OVERVIEW 96 11 2 ADM REGISTER 97 11 3 ADR REGISTERS 97 11 4 ADB REGISTERS 97 11 5 P4CON REGISTE...

Page 7: ...ITION BOARD TO EASY WRITER 117 16 5 OTP PROGRAMMING PIN TO TRANSITION BOARD MAPPING 118 16 5 1 The pin assignment of Easy and MP EZ Writer transition board socket 118 16 5 2 The pin assignment of Writ...

Page 8: ...k RC type 16KHz 3V 32KHz 5V Normal mode Both high and low clock active One channel 7 bit DAC Slow mode Low clock only Sleep mode Both high and low clock stop Powerful instructions One clocks per instr...

Page 9: ...K at 16Mhz 4bit PWM up to 1000K at 16Mhz PWM Resolution 8bit 6bit 5bit 4bit 8bit PWM up to 7 8125K at 16Mhz 4bit PWM up to 125K at 16Mhz Programmable Open Drain Output N A P1 0 P1 1 P5 2 SO B0MOV M I...

Page 10: ...ER ALU ACC INTERRUPT CONTROL TIMER COUNTER PORT 0 PORT 2 PORT 4 PORT 5 FLAGS DAC ADC DAO AIN0 AIN7 Internal CLK PWM1 PWM0 PWM0 Buzzer0 PWM1 Buzzer1 Low Volt Detector Watch Dog Timer PC IR OTP ROM H OS...

Page 11: ...IN4 7 12 VDD P4 3 AIN3 8 11 P4 0 AIN0 P4 2 AIN2 9 10 P4 1 AIN1 SN8P27142P SN8P27142S 1 3 2 SN8P27143 Pin Assignment P2 0 1 U 20 P0 1 P2 1 2 19 P0 0 P5 6 XOUT 3 18 P5 0 XIN 4 17 P5 1 VSS 5 16 P5 3 BZ1...

Page 12: ...4 3 AIN3 P2 2 10 19 P4 4 AIN4 P2 3 11 18 P4 5 AIN5 P2 4 12 17 P4 6 AIN6 P5 6 XOUT 13 16 P4 7 AIN7 XIN 14 15 VSS SN8P2714K SN8P2714S 1 3 4 SN8P2715P Pin Assignment P5 5 1 U 32 DAO P5 4 BZ0 PWM0 2 31 P0...

Page 13: ...trigger input P5 4 PWM0 BZ0 P5 3 PWM1 BZ1 AVREFH I ADC highest reference voltage input NOTE The ADC reference voltage AVREFH of SN8P27142 and SN8P27143 are VDD DAO O Current type DAC output P0 3 RST...

Page 14: ...t 0 1 and P0 2 structure Pin Int Bus Int Rst Pull Up PnUR Port 0 3 structure Pin Ext Reset Code Option Int Bus Int Rst Port 2 5 structure Pull Up Pin Output Latch PnM PnUR Input Bus PnM Output Bus Por...

Page 15: ...c 2 Instruction cycle is 2 oscillator clocks Notice In Fosc 2 Noise Filter must be disabled Fosc 4 Instruction cycle is 4 oscillator clocks Fcpu Fosc 8 Instruction cycle is 8 oscillator clocks Enable...

Page 16: ...rds reserved area 2K words All of the program memory is partitioned into three coding areas The 1st area is located from 00H to 07H The Reset vector area the 2nd area is for the interrupt vector 0008H...

Page 17: ...d vector address area is used to execute interrupt request If any interrupt service is executed the program counter PC value is stored in stack buffer and points to 0008h of program memory to execute...

Page 18: ...B0XCH A ACCBUF B0XCH doesn t change C Z flag B0MOV A PFLAG B0MOV PFLAGBUF A Save PFLAG register in a buffer User code User code B0MOV A PFLAGBUF B0MOV PFLAG A Restore PFLAG register from buffer RETI E...

Page 19: ...n ACC and high byte data stored in R register Example To look up the ROM data located TABLE1 B0MOV Y TABLE1 M To set lookup table1 s middle address B0MOV Z TABLE1 L To set lookup table1 s low address...

Page 20: ...led information Example Increase Y and Z register by B0ADD ADD instruction B0MOV Y TABLE1 M To set lookup table s middle address B0MOV Z TABLE1 L To set lookup table s low address B0MOV A BUF Z Z BUF...

Page 21: ...o A3POINT In following example the jump table starts at 0x00FD When execute B0ADD PCL A If ACC 0 or 1 the jump table points to the right address If the ACC is larger then 1 will cause error because PC...

Page 22: ...A BUF0 BUF0 is from 0 to 4 JMP_A 5 The number of the jump table listing is five JMP A0POINT If ACC 0 jump to A0POINT JMP A1POINT ACC 1 jump to A1POINT JMP A2POINT ACC 2 jump to A2POINT JMP A3POINT ACC...

Page 23: ...ea The memory is located in bank 0 The bank 0 using the first 128 byte location assigned as general purpose area and the remaining 128 byte in bank 0 as system register RAM location 000h 000h 07Fh of...

Page 24: ...R W R W R W R W Z initial value XXXX XXXX 083H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Z ZBIT7 ZBIT6 ZBIT5 ZBIT4 ZBIT3 ZBIT2 ZBIT1 ZBIT0 R W R W R W R W R W R W R W R W The YZ that is data po...

Page 25: ...OOK UP TABLE DESCRIPTION about R register look up table application 3 4 PROGRAM FLAG The PFLAG includes reset flag low voltage detect flag carry flag decimal carry flag DC and zero flag Z If the resul...

Page 26: ...ction with shifting out logic 0 3 4 5 DECIMAL CARRY FLAG DC 1 If executed arithmetic addition with occurring carry signal from low nibble or executed arithmetic subtraction without borrow signal from...

Page 27: ...e data into ACC MOV A 0FH Write ACC data from BUF data memory MOV A BUF The ACC value don t store in any interrupt service executed ACC must be exchanged to another data memory defined by users Thus o...

Page 28: ...to store program counter PC data Figure 3 3 Stack Operation STACK BUFFER STK7H STK6H STK5H STK4H STK3H STK2H STK1H STK0H STK7L STK6L STK5L STK4L STK3L STK2L STK1L STK0L STKP 0 STKP 1 STKP 2 STKP 3 STK...

Page 29: ...vice routine Stack operation is a LIFO type Last in and first out The stack pointer STKP and stack buffer STKnH and STKnL are located in the system register area bank 0 STKP stack pointer initial valu...

Page 30: ...1 STK2H STK2L 3 1 0 0 STK3H STK3L 4 0 1 1 STK4H STK4L 5 0 1 0 STK5H STK5L 6 0 0 1 STK6H STK6L 7 0 0 0 STK7H STK7L 8 Stack Overflow Table 3 1 STKP STKnH and STKnL relative of Stack Save Operation The...

Page 31: ...execution Besides it can be replaced with specific address by executing CALL or JMP instruction When JMP or CALL instruction is executed the destination address will be inserted to bit 0 bit 10 PC Ini...

Page 32: ...TEP Else jump to C1STEP C1STEP NOP If the ACC is equal to the immediate data or memory the PC will add 2 steps to skip next instruction CMPRS A 12H Skip next instruction if ACC 12H JMP C0STEP Else jum...

Page 33: ...signal occurs after execution of ADD PCL A the carry signal will not affect PCH register Example If PC 0323H PCH 03H PCL 23H PC 0323H MOV A 28H B0MOV PCL A Jump to address 0328H PC 0328H MOV A 00H B0M...

Page 34: ...sing mode MOV A 12H To set an immediate data 12H into ACC 4 1 2 DIRECTLY ADDRESSING MODE The directly addressing mode uses address number to access memory location MOV A 12H MOV 12H A Directly address...

Page 35: ...cess methods Example 1 To use RAM bank0 dedicate instruction Such as B0xxx instruction B0MOV A 12H To move content from location 12H of RAM bank 0 to ACC Example 2 To use indirectly addressing mode wi...

Page 36: ...data buffer DAM DAC s mode register Y Z Working YZ and ROM addressing register ADB ADC s data buffer ADM ADC s mode register PnM Port n input output mode register ADR ADC s resolution selects registe...

Page 37: ...INTEN 0CAH CPUM0 CLKMD STPHX R W OSCM 0CCH WDTR7 WDTR6 WDTR5 WDTR4 WDTR3 WDTR2 WDTR1 WDTR0 W WDTR 0CDH TC0R7 TC0R6 TC0R5 TC0R4 TC0R3 TC0R2 TC0R1 TC0R0 W TC0R 0CEH PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 R W...

Page 38: ...PC1 S2PC0 R W STK2L 0FBH S2PC10 S2PC9 S2PC8 R W STK2H 0FCH S1PC7 S1PC6 S1PC5 S1PC4 S1PC3 S1PC2 S1PC1 S1PC0 R W STK1L 0FDH S1PC10 S1PC9 S1PC8 R W STK1H 0FEH S0PC7 S0PC6 S0PC5 S0PC4 S0PC3 S0PC2 S0PC1 S0...

Page 39: ...e system provides complete procedures to make the power on reset successful For different oscillator types the reset time is different That causes the VDD rise rate and start up time of different osci...

Page 40: ...dog timer by program Under error condition system is in unknown situation and watchdog can t be clear by program before watchdog timer overflow Watchdog timer overflow occurs and the system is reset A...

Page 41: ...V1 doesn t touch the below area and not effect the system operation But the V2 and V3 is under the below area and may induce the system error occurrence Let system under dead band includes some condi...

Page 42: ...minimum operating voltage rises when the system executing rate upper even higher than system reset voltage The dead band definition is the system minimum operating voltage above the system reset volta...

Page 43: ...d band and the execution error the watchdog timer can t be clear by program The watchdog is continuously counting until overflow occurrence The overflow signal of watchdog timer triggers the system to...

Page 44: ...l the system keeps reset status and waits external reset pin released z System initialization All system registers is set as initial conditions and system is ready z Oscillator warm up Oscillator oper...

Page 45: ...rcuit and Diode RC reset circuit is necessary to limit any current flowing into reset pin from external capacitor C in the event of reset pin breakdown due to Electrostatic Discharge ESD or Electrical...

Page 46: ...ght R1 R2 value to conform the application In the circuit diagram condition the MCU s reset pin level varies with VDD voltage variation and the differential voltage is 0 7V If the VDD drops and the vo...

Page 47: ...VDD VSS VCC GND RST Reset IC VDD VSS RST Bypass Capacitor 0 1uF The external reset circuit also use external reset IC to enhance MCU reset performance This is a high cost and good effect solution By...

Page 48: ...or circuit Figure 7 1 System Clock Block Diagram z Fosc Fhosc External high clock in normal mode z Fosc Flosc Internal low RC clock in slow mode z Fosc is system clock Fcpu is instruction cycle clock...

Page 49: ...ard crystal resonator mode 4M code option For different application the users can select one of suitable oscillator mode by programming High_Clk code option to generate system high speed clock source...

Page 50: ...ure 7 4 External clock input Note1 The VDD and VSS of external oscillator circuit must be from the micro controller Don t connect them from the neighbor power terminal Note2 The external clock input m...

Page 51: ...truction cycle Fcpu We can get the Fosc frequency of external RC from the Fcpu frequency The sub routine to get Fcpu frequency of external oscillator is as the following Example Fcpu instruction cycle...

Page 52: ...cted by the voltage and temperature of the system In common condition the frequency of the RC oscillator is about 16KHz at 3V and 32KHz at 5V The relative between the RC frequency and voltage is as fo...

Page 53: ...system switch to slow mode In slow mode the system works as normal mode but the slower clock The system in slow mode can get into normal mode and power down mode To set STPHX 1 to stop the external h...

Page 54: ...Inactive Active by program Watchdog timer Active Active By Watchdog code option Internal interrupt All active All active All inactive External interrupt All active All active All inactive Wakeup sourc...

Page 55: ...for power saving Note To stop high speed oscillator is not necessary and user can omit it Switch slow mode to normal mode The external high speed oscillator is still running B0BCLR FCLKMD To set CLKMD...

Page 56: ...2 HARDWARE WAKEUP When the system is in power down mode sleep mode the external high speed oscillator stops For wakeup into normal SN8P2710 provides 4096 external high speed oscillator clocks to be t...

Page 57: ...al low speed RC oscillator The overflow time of WDT is about 1 16K 512 16 0 5s 3V 1 32K 512 16 0 25s 5V 0CCH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 WDTR WDTR7 WDTR6 WDTR5 WDTR4 WDTR3 WDTR2 WD...

Page 58: ...ed by counter logic Figure 8 1 Timer Count TC0 Block Diagram The main purposes of the TC0 timer counter is as following 8 bit programmable timer Generates interrupts at specific time intervals based o...

Page 59: ...came from Fcpu 1 TC1 clock came from Fosc Bit2 TC0X8 Multiple TC0 timer speed eight times Refer TC0M register for detailed information 0 TC0 clock came from Fcpu 1 TC0 clock came from Fosc Note Under...

Page 60: ...unt 0 1 3Fh to 40h 0 64 63 64 31 25K Overflow per 64 count 1 0 1Fh to 20h 0 32 31 32 62 5K Overflow per 32 count 1 1 0Fh to 10h 0 16 15 16 125K Overflow per 16 count PWM0OUT 1 TC0X8 1 ALOAD0 TC0OUT TC...

Page 61: ...Under TC0 interrupt service request TC0IEN enable condition the TC0 interrupt request flag will be set 1 and the system executes the interrupt service routine TC0C initial value xxxx xxxx 0DBH Bit 7 B...

Page 62: ...ms 2 23us 62 5 ms 0 24 ms 110 fcpu 4 0 285 ms 1 11us 31 25 ms 0 12 ms 111 fcpu 2 0 143 ms 0 56 us 15 63 ms 0 06 ms TC0_Counter 5 bit TC0X8 0 High speed mode fcpu 3 58MHz 4 Low speed mode fcpu 32768Hz...

Page 63: ...ain purpose of TC0R is as following Store the auto reload value and set into TC0C when the TC0C overflow ALOAD0 1 Store the duty value of PWM0OUT function TC0R initial value xxxx xxxx 0CDH Bit 7 Bit 6...

Page 64: ...auto reload function B0BCLR FTC0IEN To disable TC0 interrupt service B0BCLR FTC0ENB To disable TC0 timer MOV A 00H B0MOV TC0M A To set TC0 clock fcpu 256 MOV A 74H To set TC0C initial value 74H B0MOV...

Page 65: ...rvice routine and exit interrupt vector EXIT_INT B0MOV A PFLAGBUF B0MOV PFLAG A Restore PFLAG register from buffer B0XCH A ACCBUF Restore ACC value RETI Exit interrupt vector Example TC0 interrupt ser...

Page 66: ...zzer output to output multi frequency Figure 8 2 The TC0OUT Pulse Frequency Example Setup TC0OUT output from TC0 to TC0OUT P5 4 The Fcpu is 4MHz The TC0OUT frequency is 1KHz Because the TC0OUT signal...

Page 67: ...ncremented by counter logic Figure 8 3 Timer Count TC1 Block Diagram The main purposes of the TC1 timer is as following 8 bit programmable timer Generates interrupts at specific time intervals based o...

Page 68: ...rom Fcpu 1 TC1 clock came from Fosc Bit2 TC0X8 Multiple TC0 timer speed eight times Refer TC0M register for detailed information 0 TC0 clock came from Fcpu 1 TC0 clock came from Fosc Note Under TC1 ev...

Page 69: ...unt 0 1 3Fh to 40h 0 64 63 64 31 25K Overflow per 64 count 1 0 1Fh to 20h 0 32 31 32 62 5K Overflow per 32 count 1 1 0Fh to 10h 0 16 15 16 125K Overflow per 16 count PWM0OUT 1 TC1X8 1 ALOAD0 TC0OUT TC...

Page 70: ...e request TC1IEN enable condition the TC1 interrupt request flag will be set 1 and the system executes the interrupt service routine TC1C initial value xxxx xxxx 0DDH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit...

Page 71: ...ms 2 23us 62 5 ms 0 24 ms 110 fcpu 4 0 285 ms 1 11us 31 25 ms 0 12 ms 111 fcpu 2 0 143 ms 0 56 us 15 63 ms 0 06 ms TC1_Counter 5 bit TC1X8 0 High speed mode fcpu 3 58MHz 4 Low speed mode fcpu 32768Hz...

Page 72: ...ain purpose of TC1R is as following Store the auto reload value and set into TC1C when the TC1C overflow ALOAD1 1 Store the duty value of PWM1OUT function TC1R initial value xxxx xxxx 0DEH Bit 7 Bit 6...

Page 73: ...n B0BCLR FTC1IEN To disable TC1 interrupt service B0BCLR FTC1ENB To disable TC1 timer B0BCLR FTC1X8 MOV A 00H B0MOV TC1M A To set TC1 clock fcpu 256 MOV A 74H To set TC1C initial value 74H B0MOV TC1C...

Page 74: ...e routine and exit interrupt vector EXIT_INT B0MOV A PFLAGBUF B0MOV PFLAG A Restore PFLAG register from buffer B0XCH A ACCBUF Restore ACC value RETI Exit interrupt vector Example TC1 interrupt service...

Page 75: ...OUT Pulse Frequency Example Setup TC1OUT output from TC1 to TC1OUT P5 3 The Fcpu is 4MHz The TC1OUT frequency is 1KHz Because the TC1OUT signal is divided by 2 set the TC1 clock to 2KHz The TC1 clock...

Page 76: ...PWM output to high level except for the last pulse of the clock source which sends the output low PWM0OUT 1 TC0X8 0 ALOAD0 ALOAD1 TC0OUT TC1OUT TC0 Overflow boundary TC1 Overflow boundary PWM duty ra...

Page 77: ...4 I O function B0BSET FTC0ENB Enable TC0 timer Note1 The TC0R and TC1R are write only registers Don t process them using INCMS DECMS instructions Note2 Set TC0C at initial is to make first duty cycle...

Page 78: ...changing in the program processing the PWM waveform will became In period 2 and period 4 new Duty TCxR is set However the PWM still keep the same duty in period 2 and period 4 and the duty changed in...

Page 79: ...x clock 256 0 1 3Fh to 40h 0 64 63 64 TCx clock 64 1 0 1Fh to 20h 0 32 31 32 TCx clock 32 1 1 0Fh to 10h 0 16 15 16 TCx clock 16 From following diagram the TC0IRQ frequency is related with PWM duty TC...

Page 80: ...must enable at first and all interrupt operations work 9 2 INTEN INTERRUPT ENABLE REGISTER INTEN is the interrupt request control register including two internal interrupts two external interrupts On...

Page 81: ...6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 INTRQ TC1IRQ TC0IRQ P01IRQ P00IRQ R W R W R W R W Bit 6 TC1IRQ TC1 timer interrupt request controls bit 0 Non request from TC1 1 Request from TC1 Bit 5 TC0IRQ TC...

Page 82: ...1 It is necessary for interrupt service request One of the interrupt requests occurs and the program counter PC points to the interrupt vector ORG 8 and the stack add 1 level STKP initial value 0xxx 1...

Page 83: ...RVICE B0XCH A ACCBUF B0XCH doesn t change C Z flag B0MOV A PFLAG B0MOV PFLAGBUF A Save PFLAG register in a buffer B0BTS1 FP00IRQ Check P00IRQ JMP EXIT_INT P00IRQ 0 exit interrupt vector B0BCLR FP00IRQ...

Page 84: ...RVICE B0XCH A ACCBUF B0XCH doesn t change C Z flag B0MOV A PFLAG B0MOV PFLAGBUF A Save PFLAG register in a buffer B0BTS1 FP01IRQ Check P01IRQ JMP EXIT_INT P01IRQ 0 exit interrupt vector B0BCLR FP01IRQ...

Page 85: ...B0BCLR FTC0ENB Disable TC0 timer MOV A 20H B0MOV TC0M A Set TC0 clock Fcpu 64 MOV A 74H Set TC0C initial value 74H B0MOV TC0C A Set TC0 interval 10 ms B0BSET FTC0IEN Enable TC0 interrupt service B0BCL...

Page 86: ...B0BCLR FT C1ENB Disable TC1 timer MOV A 20H B0MOV TC1M A Set TC1 clock Fcpu 64 MOV A 74H Set TC1C initial value 74H B0MOV TC1C A Set TC1 interval 10 ms B0BSET FTC1IEN Enable TC1 interrupt service B0BC...

Page 87: ...flags can be triggered by the events without interrupt enable Just only any the event occurs and the IRQ will be logic 1 The IRQ and its trigger event relationship is as the below table Interrupt Nam...

Page 88: ...ne INTP01CHK Check INT1 interrupt request B0BTS1 FP01IEN Check P01IEN JMP INTTC0CHK Jump check to next interrupt B0BTS0 FP01IRQ Check P01IRQ JMP INTP01 Jump to INT1 interrupt service routine INTTC0CHK...

Page 89: ...register and register PnUR is defined for user setting pull up register After the system resets all ports work as input function without pull up resistors Port 0 1 and P0 2 structure Pin Int Bus Int R...

Page 90: ...clock input pin External interrupt INT0 INT1 P0 0 P0 1 I Wakeup for power down mode General purpose input function P0 2 I Wakeup for power down mode General purpose input function No pull up No wakeup...

Page 91: ...5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P2UR P27r P26R P25R P24R P23R P22R P21R P20R Read Write W W W W W W W W After reset 0 0 0 0 0 0 0 0 Port4 0E4H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P4UR P47...

Page 92: ...7 0 P2 7 0 M P2 0 P2 7 I O direction control bit 0 Set P2 as input mode 1 Set P2 as output mode P4M initial value 0000 0000 0C4H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P4M P47M P46M P45M P44...

Page 93: ...t ADC SONiX TECHNOLOGY CO LTD Page 93 V1 4 Example I O mode selecting CLR P2M CLR P4M CLR P5M MOV A 0FFH Set all ports to be output mode B0MOV P2M A B0MOV P4M A B0MOV P5M A B0BCLR P2M 5 Set P2 5 to be...

Page 94: ...W P4 initial value xxxx xxxx 0D4H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P4 P47 P46 P45 P44 P43 P42 P41 P40 R W R W R W R W R W R W R W R W P5 initial value xxxx xxxx 0D5H Bit 7 Bit 6 Bit 5 B...

Page 95: ...iX TECHNOLOGY CO LTD Page 95 V1 4 Example Write one bit data to output port B0BSET P2 3 Set P2 3 and P4 0 to be 1 B0BSET P4 0 B0BCLR P2 3 Set P2 3 and P5 5 to be 0 B0BCLR P5 5 Example Port bit test B0...

Page 96: ...4 AIN1 P4 1 AIN6 P4 6 AIN7 P4 7 A D CONVERTER ADC AIN0 P4 0 AIN0 P4 0 AIN5 P4 5 AIN5 P4 5 AIN2 P4 2 AIN2 P4 2 AIN3 P4 3 AIN3 P4 3 AIN4 P4 4 AIN4 P4 4 AIN1 P4 1 AIN1 P4 1 AIN6 P4 6 AIN6 P4 6 AIN7 P4 7...

Page 97: ...5 110 AIN6 111 AIN7 11 3 ADR REGISTERS ADR initial value x00x 0000 0B3H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ADR ADCKS1 ADCKS0 ADB3 ADB2 ADB1 ADB0 R W R W R R R R Bit 6 4 ADCKS 1 0 ADC s cl...

Page 98: ...O O O O O Selected x Delete 11 5 P4CON REGISTERS ADB initial value 0000 0000 0AEH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P4CON P4CON7 P4CON6 P4CON5 P4CON4 P4CON3 P4CON2 P4CON1 P4CON0 W W W W...

Page 99: ...unction can work in slow mode also In slow mode the Fcpu LXOSC 4 LXOSC is internal low RC oscillator Note Because the frequency of LXOSC internal low RC oscillator will vary with different temperature...

Page 100: ...x and AVREFH Circuit of AD Converter Note The capacitor between AIN and GND is a bypass capacitor It is helpful to stable the analog signal Users can omit it VDD AVREF AIN0 P40 Analog Signal Input 0 1...

Page 101: ...DAO pin LADDER RESISTORS DAM REGISTER DAO OUTPUT LADDER RESISTORS DAM REGISTER DAO OUTPUT Figure 12 1 The DA converter Block Diagram In order to get a proper linear output a Loading Resistor RL is us...

Page 102: ...ata 12 3 D A CONVERTER OPERATION When the DAENB 0 the DAO pin is output floating status After setting DAENB to 1 the DAO output value is controlled by DAB bits Example Output 1 2 VDD from DAO pin MOV...

Page 103: ...D MACRO2 H INCLUDESTD MACRO3 H list Enable the listing function Constants Definition ONE EQU 1 Variables Definition DATA org 0h Bank 0 data section start from RAM address 0x000 Wk00B0 DS 1 Temporary b...

Page 104: ...A 00h Initial system mode b0mov OSCM A mov A 0x5A b0mov WDTR A Clear watchdog timer call ClrRAM Clear RAM call SysInit System initial b0bset FGIE Enable global interrupt Main routine Main mov A 0x5A...

Page 105: ...LAG B0MOV PFLAGBUF A Check which interrupt happen IntP00Chk b0bts1 FP00IEN jmp IntTc0Chk Modify this line for another interrupt b0bts0 FP00IRQ jmp P00isr If necessary insert another interrupt checking...

Page 106: ...vice routine TC0isr b0bclr FTC0IRQ Process TC0 timer interrupt here jmp IsrExit SysInit Initialize I O Timer Interrupt etc SysInit ret ClrRAM Use index YZ to clear RAM 00h 7Fh ClrRAM RAM Bank 0 clr Y...

Page 107: ...RAM Non Used I O Non used I O ports should be pull up or pull down in input mode or be set as low in output mode to save current consumption Sleep Mode Enable on chip pull up resistors of port 0 to a...

Page 108: ...I 1 G OR A M A A or M 1 I OR M A M A or M 1 N C OR A I A A or I 1 XOR A M A A xor M 1 XOR M A M A xor M 1 N XOR A I A A xor I 1 SWAP M A b3 b0 b7 b4 M b7 b4 b3 b0 1 P SWAPM M M b3 b0 b7 b4 M b7 b4 b3...

Page 109: ...age current Ilekg Vin Vdd 40 C 85 C 5 uA Vin Vss Vdd 3V 100 200 300 K I O port pull up resistor Rup Vin Vss Vdd 5V 50 100 180 K I O port input leakage current Ilekg Pull up resistor disable Vin Vdd 2...

Page 110: ...r design reference not tested 15 3 CHARACTERISTIC GRAPHS The Graphs in this section are for design guidance not tested or guaranteed In some graphs the data presented are outside specified operating r...

Page 111: ...ORT5 1 2 1 4 1 6 1 8 2 0 2 2 2 4 40 0 25 70 85 V 5V 3V VIH PORT4 1 2 1 4 1 6 1 8 2 0 2 2 2 4 40 0 25 70 85 V 5V 3V VIL PORT4 1 2 1 4 1 6 1 8 2 0 2 2 2 4 40 0 25 70 85 V 5V 3V Driving current ALL PORT...

Page 112: ...hosc VDD V Fcpu Fosc 4 Noise Filter Enable 40 85 2 0 2 5 3 0 3 5 4 0 4 5 5 0 5 5 4MHZ 8MHZ 12MHZ 16MHZ Fhosc VDD V Fcpu Fosc 1 Noise Filter Disable 0 70 2 0 2 5 3 0 3 5 4 0 4 5 5 0 5 5 4MHZ 8MHZ 12MHZ...

Page 113: ...it ADC SONiX TECHNOLOGY CO LTD Page 113 V1 4 Fcpu Fosc 4 Noise Filter Disable 0 70 2 0 2 5 3 0 3 5 4 0 4 5 5 0 5 5 4MHZ 8MHZ 12MHZ 16MHZ Fhosc VDD V Fcpu Fosc 4 Noise Filter Enable 0 70 2 0 2 5 3 0 3...

Page 114: ...P2714X and SN8P2715 serial emulation 16 1 2 OTP Writer z Writer 3 0 Support SN8P2715 SN8P2714 but no Stand alone mode z Easy Writer V1 0 OTP programming is controlled by ICE without firmware upgrade s...

Page 115: ...board for ICE emulation The EV Kit provide LVD2 4V 3 6V selection circuit emulation CON1 and JP3 ICE I O interface S1 VD 2 4V and LVD 3 6V trigger control To emulate LVD 2 4V flag reset function and L...

Page 116: ...ection from SN8P2715 14 EV KIT to SN8ICE 2K is as following SN8ICE2K ICE emulation notice a Operation voltage of ICE 3 0V 5 0V b Recommend maximum emulation speed at 5V 8 MIPS e g 16MHZ crystal and Fc...

Page 117: ...P2715 2714 Rev B transition board is for SN8P2715 2714 OTP programming including P DIP 20 pins and P DIP 18 pins Rev B transition board and EV Kit is the same board JP2 Connect to Easy writer or MP EZ...

Page 118: ...6 14 13 D7 DIP7 7 42 DIP42 VPP 16 15 VDD DIP8 8 41 DIP41 RST 18 17 HLS DIP9 9 40 DIP40 ALSB PDB 20 19 DIP10 10 39 DIP39 DIP11 11 38 DIP38 JP1 for MP transition board DIP12 12 37 DIP38 JP2 for Writer V...

Page 119: ...And Writer V3 0 OTP IC JP3 Pin Assignment Number Pin Number Pin Number Pin Number Pin Number Pin 1 VDD 25 VDD 30 VDD 12 VDD 13 VDD 2 GND 15 VSS 20 VSS 6 VSS 5 VSS 3 CLK 4 P5 0 6 P5 0 17 P5 0 18 P5 0...

Page 120: ...production definition of all 8 bit MCU for order or obtain information This definition is only for Blank OTP MCU 17 2 MARKING INDETIFICATION SYSTEM SN8 X PART No X X X Title SONiX 8 bit MCU Productio...

Page 121: ...ask 1708A SSOP 0 70 N A Note Industrial Level production didn t support Wafer or Dice shipping type 17 4 DATECODE SYSTEM There are total 8 9 letters of SONiX datecode system The final four or five cha...

Page 122: ...it ADC SONiX TECHNOLOGY CO LTD Page 122 V1 4 18 PACKAGE INFORMATION 18 1 P DIP18 PIN Symbols MIN NOR MAX A 0 210 A1 0 015 A2 0 125 0 130 0 135 D 0 880 0 900 0 920 E 0 300BSC E1 0 245 0 250 0 255 L 0 1...

Page 123: ...5 8 bit micro controller build in 12 bit ADC SONiX TECHNOLOGY CO LTD Page 123 V1 4 18 2 SOP18 PIN Symbols MIN MAX A 0 093 0 104 A1 0 004 0 012 D 0 447 0 463 E 0 291 0 299 H 0 394 0 419 L 0 016 0 050 0...

Page 124: ...SN8P2714X_2715 8 bit micro controller build in 12 bit ADC SONiX TECHNOLOGY CO LTD Page 124 V1 4 18 3 P DIP 20 PIN...

Page 125: ...SN8P2714X_2715 8 bit micro controller build in 12 bit ADC SONiX TECHNOLOGY CO LTD Page 125 V1 4 18 4 SOP 20 PIN...

Page 126: ...60 1 75 53 63 69 A1 0 10 0 15 0 25 4 6 10 A2 1 50 59 b 0 20 0 254 0 30 8 10 12 b1 0 20 0 254 0 28 8 11 11 C 0 18 0 203 0 25 7 8 10 C1 0 18 0 203 0 23 7 8 9 D 8 56 8 66 8 74 337 341 344 E 5 80 6 00 6...

Page 127: ...ild in 12 bit ADC SONiX TECHNOLOGY CO LTD Page 127 V1 4 18 6 SK DIP28 PIN Symbols MIN NOR MAX A 0 210 A1 0 015 A2 0 114 0 130 0 135 D 1 390 1 390 1 400 E 0 310BSC E1 0 283 0 288 0 293 L 0 115 0 130 0...

Page 128: ...5 8 bit micro controller build in 12 bit ADC SONiX TECHNOLOGY CO LTD Page 128 V1 4 18 7 SOP28 PIN Symbols MIN MAX A 0 093 0 104 A1 0 004 0 012 D 0 697 0 713 E 0 291 0 299 H 0 394 0 419 L 0 016 0 050 0...

Page 129: ...SN8P2714X_2715 8 bit micro controller build in 12 bit ADC SONiX TECHNOLOGY CO LTD Page 129 V1 4 18 8 P DIP 32 PIN 18 9 SOP 32 PIN...

Page 130: ...or death may occur Should Buyer purchase or use SONIX products for any such unintended or unauthorized application Buyer shall indemnify and hold SONIX and its officers employees subsidiaries affiliat...

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