SN8P2714X_2715
8-bit micro-controller build-in 12-bit ADC
SONiX TECHNOLOGY CO., LTD
Page 80
V1.4
9
INTERRUPT
9.1 OVERVIEW
The SN8P2710 provides 4 interrupt sources, including two internal interrupts (TC0, TC1) and two external interrupts
(INT0, INT1). These external interrupts can wakeup the chip from power down mode to high-speed normal mode. The
external clock input pins of INT0/INT1 are shared with P0.0/P0.1 pins. Once interrupt service is executed, the GIE bit in
STKP register will clear to “0” for stopping other interrupt request. When interrupt service exits, the GIE bit will set to “1”
to accept the next interrupts’ request. All of the interrupt request signals are stored in INTRQ register. The user can
program the chip to check INTRQ’s content for setting executive priority.
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Note: 1.The GIE bit must enable at first and all interrupt operations work.
9.2 INTEN INTERRUPT ENABLE REGISTER
INTEN is the interrupt request control register including two internal interrupts, two external interrupts. One of the
register to be set “1” is to enable the interrupt request function. Once of the interrupt occur, the program jump to ORG
8 to execute interrupt service routines. The program exits the interrupt service routine when the returning interrupt
service routine instruction (RETI) is executed.
INTEN initial value = 0000 0000
0C9H
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTEN
- TC1IEN
TC0IEN -
-
- P01IEN
P00IEN
- R/W
R/W - - - R/W
R/W
Bit 6
TC1IEN:
Timer interrupt control bit.
0 = Disable TC1 Interrupt
1 = Enable TC1 Interrupt
Bit 5
TC0IEN:
Timer interrupt control bit.
0 = Disable TC0 Interrupt
1 = Enable TC10Interrupt
Bit 1
P01IEN:
External P0.1 interrupt control bit.
0 = Disable P01 Interrupt
1 = Enable P01 Interrupt
Bit 0
P00IEN:
External P0.0 interrupt control bit.
0 = Disable P00 Interrupt
1 = Enable P00 Interrupt
