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SN8P2604

8-Bit Micro-Controller

SONiX TECHNOLOGY CO., LTD

Page 97

Version 1.1

11.5.2 INSTRUCTION CYCLE

Instruction cycles of some instructions are different between SN8P2604 and EV chip. These differences makes ICE
instruction timing isn’t consistent with SN8P2604. SN8IDE assembler provides some macros to solve instruction cycle
difference as following. Users just only use built-in instruction macro to replace corresponding instruction. In
“ICE_MODE EQU 1” ICE emulation mode, assembler maybe insert some extra code to synchronize instruction timing
between ICE and real chip. Therefore, the maximum available ROM size is larger than real chip. In “ICE_MODE EQU
0” the ROM size is same as real chip.

SN8P2604

S8KD-2 EV CHIP

Field Mnemonic Cycle

Field

Mnemonic Cycle

INSTRUCTION

MACRO

DESCRIPTION

MOV

A,M

1

MOV

A,M

1

-

M

MOV

M,A

1

M

MOV

M,A

1

-

O

B0MOV A,M 1 O

B0MOV A,M 1

-

V

B0MOV M,A 1 V

B0MOV M,A 1

-

E

MOV

A,I

1

E

MOV

A,I

1

-

B0MOV

M,I

1

B0MOV

M,I

1

-

XCH

A,M

1+N

XCH

A,M

1

@XCH A,M

B0XCH

A,M

1+N

B0XCH

A,M

1

@B0XCH A,M

MOVC

2

MOVC

2

-

ADC

A,M

1

ADC

A,M

1

-

A

ADC

M,A

1+A

A

ADC

M,A

1

@ADC M,A

R

ADD

A,M

1

R

ADD

A,M

1

-

I

ADD

M,A

1+N

I

ADD

M,A

1

@ADD M,A

T

B0ADD

M,A

1+N

T

B0ADD

M,A

1

@B0ADD M,A

H

ADD

A,I

1

H

ADD

A,I

1

-

M

SBC

A,M

1

M

SBC

A,M

1

-

E

SBC

M,A

1+N

E

SBC

M,A

1

@SBC M,A

T

SUB

A,M

1

T

SUB

A,M

1

-

I

SUB

M,A

1+N

I

SUB

M,A

1

@SUB M,A

C

SUB

A,I

1

C

SUB

A,I

1

-

AND

A,M

1

AND

A,M

1

-

L

AND

M,A

1+N

L

AND

M,A

1

@AND M,A

O

AND

A,I

1

O

AND

A,I

1

-

G

OR

A,M

1

G

OR

A,M

1

-

I

OR

M,A

1+N

I

OR

M,A

1

@OR M,A

C

OR

A,I

1

C

OR

A,I

1

-

XOR

A,M

1

XOR

A,M

1

-

XOR

M,A

1+N

XOR

M,A

1

@XOR M,A

XOR

A,I

1

XOR

A,I

1

-

SWAP

M

1

SWAP

M

1

-

P

SWAPM

M

1+N

P

SWAPM

M

1

@SWAPM M

R

RRC

M

1

R

RRC

M

1

-

O

RRCM

M

1+N

O

RRCM

M

1

@RRCM M

C

RLC

M

1

C

RLC

M

1

-

E

RLCM

M

1+N

E

RLCM

M

1

@RLCM M

S

CLR

M

1

S

CLR

M

1

-

S

BCLR

M.b

1+N

S

BCLR

M.b

1

@BSET M.b

BSET

M.b

1+N

BSET

M.b

1

@BCLR M.b

B0BCLR

M.b

1+N

B0BCLR

M.b

1

@B0BSET M.b

B0BSET

M.b

1+N

B0BSET

M.b

1

@B0BCLR M.b

CMPRS

A,I

1 + S

CMPRS

A,I

1 + S

-

B

CMPRS

A,M

1 + S

B

CMPRS

A,M

1 + S

-

R

INCS

M

1 + S

R

INCS

M

1 + S

-

A

INCMS

M

1+N+S

A

INCMS

M

1 + S

@INCMS M

N

DECS

M

1 + S

N

DECS

M

1 + S

-

C

DECMS

M

1+N+S

C

DECMS

M

1 + S

@DECMS M

H

BTS0

M.b

1 + S

H

BTS0

M.b

1 + S

-

BTS1

M.b

1 + S

BTS1

M.b

1 + S

-

B0BTS0

M.b

1 + S

B0BTS0

M.b

1 + S

-

B0BTS1

M.b

1 + S

B0BTS1

M.b

1 + S

-

M

JMP

d

2

M

JMP

d

2

-

I

CALL

d

2

I

CALL

d

2

-

S

RET

2

S

RET

2

-

C

RETI

2

C

RETI

2

-

NOP

1

NOP

1

-

1.
M = RAM, N = 0.
M = system
register, N = 1.

2.

S8KD-2 ICE

：

Read OSCM = 1
cycle
Write OSCM = 2
cycle

SN8P2604

：

Read OSCM = 1
cycle
Write OSCM = 1
cycle

3.
PUSH,POP
instructions are
different between
SN8P2604 and
S8KD-2 ICE.

PUSH

1

PUSH

1

POP

1

POP

1

«
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95
96
97
98
99
...
»

Summary of Contents for SN8P2604

Page 1: ...as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the SONIX product c...

Page 2: ...tics ViL ViH Ilekg Rup IoH 5 Add Development Tool Version section in Application Notice chapter 6 Change chapter name TRANSITION SOCKET to OTP PROGRAMMING PIN and modify the contents 7 Remove Template...

Page 3: ...RRUPT VECTOR 0008H 16 2 1 1 3 LOOK UP TABLE DESCRIPTION 18 2 1 1 4 JUMP TABLE DESCRIPTION 20 2 1 1 5 CHECKSUM CALCULATION 22 2 1 2 CODE OPTION TABLE 23 2 1 3 DATA MEMORY RAM 24 2 1 4 SYSTEM REGISTER 2...

Page 4: ...T 42 3 5 LOW VOLTAGE DETECTOR LVD 43 4 4 4 SYSTEM CLOCK 44 4 1 OVERVIEW 44 4 2 CLOCK BLOCK DIAGRAM 44 4 3 OSCM REGISTER 45 4 4 SYSTEM HIGH CLOCK 46 4 4 1 EXTERNAL HIGH CLOCK 46 4 4 1 1 CRYSTAL CERAMIC...

Page 5: ...ON 64 6 10 MULTI INTERRUPT OPERATION 65 7 7 7 I O PORT 66 7 1 I O PORT MODE 66 7 2 I O PULL UP REGISTER 67 7 3 I O OPEN DRAIN REGISTER 68 7 4 I O PORT DATA REGISTER 69 8 8 8 TIMERS 70 8 1 WATCHDOG TIM...

Page 6: ...ERISTIC 91 1 1 11 1 1 APPLICATION NOTICE 92 11 1 DEVELOPMENT TOOL VERSION 92 11 1 1 ICE In circuit emulation 92 11 1 2 OTP Writer 92 11 1 3 SN8IDE 92 11 2 CODE OPTION 93 11 2 1 FCPU CODE OPTION 93 11...

Page 7: ...G PIN 106 12 1 1 The pin assignment of Easy Writer transition board socket 106 12 1 2 The pin assignment of Writer V3 0 and V2 5 transition board socket 106 12 1 3 SN8P2604 Programming Pin Mapping 107...

Page 8: ...0 P1 1 Wakeup P0 P1 level change trigger On chip watchdog timer and clock source is internal Pull up resisters P0 P1 P2 P5 low clock RC type 16KHz 3V 32KHz 5V External interrupt input P0 0 P0 1 Extern...

Page 9: ...PEDGE register P00G 1 0 bit4 and bit3 00 Reserved 01 Rising edge 10 Falling edge 11 Level change Controlled by PEDGE register PEDGEN bit7 0 Falling edge 1 Defined by P00G 1 0 P00G 1 0 bit4 and bit3 0...

Page 10: ...OR RAM SYSTEM REGISTER ALU ACC INTERRUPT CONTROL TIMER COUNTER PORT 0 PORT 1 FLAGS Internal Low RC POR Watch Dog SN8P2604 PWM PORT 5 PWM BUZZER PORT 2 PC IR R O M H OSC TIMING GENERATOR RAM SYSTEM REG...

Page 11: ...P5 0 6 23 P2 5 P5 1 7 22 P2 4 P5 2 8 21 P2 3 P5 3 BZ1 PWM1 9 20 P2 2 P1 0 10 19 P2 1 P1 1 11 18 P2 0 P1 2 12 17 P1 7 P1 3 13 16 P1 6 P1 4 14 15 P1 5 SN8P2604K SN8P2604S SN8P2604X SN8P26042P P DIP 20...

Page 12: ...ucture as input mode Built in pull up resisters INT0 trigger pin Schmitt trigger P0 1 INT1 I O Port 0 1 bi direction pin Schmitt trigger structure as input mode Built in pull up resisters INT1 trigger...

Page 13: ...1 1 1 5 PIN CIRCUIT DIAGRAMS Port 0 1 2 5 structure Pull Up Pin Output Latch PnM PnUR Input Bus PnM Output Bus Port 1 0 P1 1 structure Pull Up Pin Output Latch PnM PnUR Input Bus PnM Output Bus P1OC...

Page 14: ...0000H Reset vector User reset vector 0001H Jump to user start address 0002H Jump to user start address 0003H General purpose area Jump to user start address 0004H 0005H 0006H 0007H General purpose ar...

Page 15: ...ernal reset or watchdog timer overflow reset then the chip will restart the program from address 0000h and all system registers will be set as default values It is easy to know reset status from NT0 N...

Page 16: ...the way to define the interrupt vector in the program memory Note PUSH POP instructions save and load ACC PFLAG without NT0 NPD PUSH POP buffer is a unique buffer and only one level Note The first in...

Page 17: ...0010H The head of user program User program JMP START End of user program MY_IRQ The head of interrupt service routine PUSH Save ACC and PFLAG register to buffers POP Load ACC and PFLAG register from...

Page 18: ...kup table1 s middle address B0MOV Z TABLE1 L To set lookup table1 s low address MOVC To lookup data R 00H ACC 35H Increment the index address for next address INCMS Z Z 1 JMP F Z is not overflow INCMS...

Page 19: ...ord 16 bits data DW 5105H DW 2012H The other example of loop up table is to add Y or Z index register by accumulator Please be careful if carry happen Example Increase Y and Z register by B0ADD ADD in...

Page 20: ...ACC PCH adds one automatically If PCL borrow after PCL ACC PCH keeps value and not change Example Jump table ORG 0X0100 The jump table is from the head of the ROM boundary B0ADD PCL A PCL PCL ACC PCH...

Page 21: ...gin from next RAM boundary 0x0100 Example JMP_A operation Before compiling program ROM address B0MOV A BUF0 BUF0 is from 0 to 4 JMP_A 5 The number of the jump table listing is five 0X00FD JMP A0POINT...

Page 22: ...end_addr2 CLR Y Set Y to 00H CLR Z Set Z to 00H MOVC B0BSET FC Clear C flag ADD DATA1 A Add A to Data1 MOV A R ADC DATA2 A Add R to Data2 JMP END_CHECK Check if the YZ address the end of code AAA INC...

Page 23: ...r clock Notice In Fosc 1 Noise Filter must be disabled Fosc 2 Instruction cycle is 2 oscillator clocks Notice In Fosc 2 Noise Filter must be disabled Fosc 4 Instruction cycle is 4 oscillator clocks Fc...

Page 24: ...iX TECHNOLOGY CO LTD Page 24 Version 1 1 2 1 3 DATA MEMORY RAM 128 X 8 bit RAM Address RAM location 000h 07Fh General purpose area 080h 080h 0FFh of Bank 0 store system registers 128 bytes System regi...

Page 25: ...L Working HL and ROM addressing register Y Z Working YZ and ROM addressing register P1W Port 1 wakeup register PEDGE P0 0 edge direction register PnM Port n input output mode register Pn Port n data b...

Page 26: ...TC1R6 TC1R5 TC1R4 TC1R3 TC1R2 TC1R1 TC1R0 W TC1R 0DFH GIE STKPB2 STKPB1 STKPB0 R W STKP 0E0H P01R P00R W P0UR 0E1H P17R P16R P15R P14R P13R P12R P11R P10R W P1UR 0E2H P27R P26R P25R P24R P23R P22R P2...

Page 27: ...by B0MOV instruction during the instant addressing mode Example Read and write ACC value Read ACC data and store in BUF data memory MOV BUF A Write a immediate data into ACC MOV A 0FH Write ACC data...

Page 28: ...set status flag NT0 NPD Reset Status 0 0 Watch dog time out 0 1 Reserved 1 0 Reset by LVD 1 1 Reset by external Reset Pin Bit 2 C Carry flag 1 Addition with carry subtraction without borrowing rotatio...

Page 29: ...t 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PC PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 After reset 0 0 0 0 0 0 0 0 0 0 0 0 PCH PCL ONE ADDRESS SKIPPING There are nine instructi...

Page 30: ...C0STEP Jump to C0STEP if ACC is not zero C0STEP NOP INCMS instruction INCMS BUF0 JMP C0STEP Jump to C0STEP if BUF0 is not zero C0STEP NOP If the destination decreased by 1 which results underflow of 0...

Page 31: ...hree instructions and don t care PCL overflow problem Note PCH only support PC up counting result and doesn t support PC down counting When PCL is carry after PCL ACC PCH adds one automatically If PCL...

Page 32: ...it 0 L LBIT7 LBIT6 LBIT5 LBIT4 LBIT3 LBIT2 LBIT1 LBIT0 Read Write R W R W R W R W R W R W R W R W After reset X X X X X X X X Example If want to read a data from RAM address 20H of bank_0 it can use i...

Page 33: ...ter reset 083H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Z ZBIT7 ZBIT6 ZBIT5 ZBIT4 ZBIT3 ZBIT2 ZBIT1 ZBIT0 Read Write R W R W R W R W R W R W R W R W After reset Example Uses Y Z register as the...

Page 34: ...yte data of look up table MOVC instruction executed the high byte data of specified ROM address will be stored in R register and the low byte data will be stored in ACC 082H Bit 7 Bit 6 Bit 5 Bit 4 Bi...

Page 35: ...ample Move 0x12 RAM location data into ACC B0MOV A 12H To get a content of RAM location 0x12 of bank 0 and save in ACC Example Move ACC data into 0x12 RAM location B0MOV 12H A To get a content of ACC...

Page 36: ...are executed The STKP register is a pointer designed to point active level in order to push or pop up data from stack buffer The STKnH and STKnL are the stack buffers to store program counter PC data...

Page 37: ...ce routine Stack operation is a LIFO type Last in and first out The stack pointer STKP and stack buffer STKnH and STKnL are located in the system register area bank 0 0DFH Bit 7 Bit 6 Bit 5 Bit 4 Bit...

Page 38: ...0 STK2H STK2L 4 0 1 1 STK3H STK3L 5 0 1 0 STK4H STK4L 6 0 0 1 STK5H STK5L 7 0 0 0 STK6H STK6L 8 1 1 1 STK7H STK7L 8 1 1 0 Stack Over error There are Stack Restore operations correspond to each push o...

Page 39: ...eared After reset status released the system boots up and program starts to execute from ORG 0 The NT0 NPD flags indicate system reset status The system can depend on NT0 NPD status and go to differen...

Page 40: ...scillator s start up time is very short but the crystal type is longer Under client terminal application users have to take care the power on reset time for the master terminal requirement The reset t...

Page 41: ...ogram executing Power on sequence is finished and program executes from ORG 0 3 3 WATCHDOG RESET Watchdog reset is a system protection In normal condition system works well and clears watchdog timer b...

Page 42: ...the system keeps in reset status External reset sequence is as following External reset only external reset pin enable System checks external reset pin status If external reset pin is not high level t...

Page 43: ...o low voltage but not zero This condition is called Brown Out In brown out situation the external reset would be error and system can t reset by external reset and halts System should be reset in brow...

Page 44: ...on cycle Fcpu Normal Mode High Clock Fcpu Fhosc N N 1 8 Select N by Fcpu code option Slow Mode Low Clock Fcpu Flosc 4 SONIX provides a Noise Filter controlled by code option In high noisy situation th...

Page 45: ...e run stop Internal low speed RC oscillator is still running Bit 2 CLKMD System high Low clock mode control bit 0 Normal dual mode System clock is high clock 1 Slow mode System clock is internal low c...

Page 46: ...The high clock is external high speed oscillator The typical frequency is 12MHz 4M The high clock is external oscillator The typical frequency is 4MHz 4 4 1 EXTERNAL HIGH CLOCK External high clock in...

Page 47: ...ex 4MHz 32K option is for low speed ex 32768Hz MCU VCC GND C 20pF XIN XOUT VDD VSS C 20pF CRYSTAL Note Connect the Crystal Ceramic and C as near as possible to the XIN XOUT VSS pins of micro controlle...

Page 48: ...rnal clock signal input to be system clock is by RC option of High_Clk code option The external clock signal is input from XIN pin XOUT pin is general purpose I O pin MCU VCC GND VSS VDD XIN XOUT Exte...

Page 49: ...00 35 00 40 00 45 00 2 1 2 5 3 3 1 3 3 3 5 4 4 5 5 5 5 6 6 5 7 VDD V Freq KHz ILRC The internal low RC supports watchdog clock source and system slow mode controlled by CLKMD Flosc Internal low RC osc...

Page 50: ...cle Fcpu This way is useful in RC mode Example Fcpu instruction cycle of external oscillator B0BSET P0M 0 Set P0 0 to be output mode for outputting Fcpu toggle signal B0BSET P0 0 Output Fcpu toggle si...

Page 51: ...0 Timer Time Out External Reset Circuit Active System Mode Switching Diagram Operating mode description MODE NORMAL SLOW GREEN POWER DOWN SLEEP REMARK EHOSC Running By STPHX By STPHX Stop ILRC Running...

Page 52: ...or is still running B0BCLR FCLKMD To set CLKMD 0 Example Switch slow mode to normal mode The external high speed oscillator stops If external high clock stop and program want to switch back normal mod...

Page 53: ...A To set T0 clock Fcpu 64 MOV A 74H B0MOV T0C A To set T0C initial value 74H To set T0 interval 10 ms B0BCLR FT0IEN To disable T0 interrupt service B0BCLR FT0IRQ To clear T0 interrupt request B0BSET F...

Page 54: ...IME When the system is in power down mode sleep mode the high clock oscillator stops When waked up from power down mode MCU waits for 2048 external high speed oscillator clocks as the wakeup time to s...

Page 55: ...tem up to normal mode The Port 0 and Port 1 have wakeup function Port 0 wakeup function always enables but the Port 1 is controlled by the P1W register 0C0H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 B...

Page 56: ...pt service is executed the GIE bit in STKP register will clear to 0 for stopping other interrupt request On the contrast when interrupt service exits the GIE bit will set to 1 to accept the next inter...

Page 57: ...outine when the returning interrupt service routine instruction RETI is executed 0C9H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 INTEN TC1IEN T0IEN P01IEN P00IEN Read Write R W R W R W R W After...

Page 58: ...t requests occurring by the register and do the routine corresponding of the interrupt request 0C8H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 INTRQ TC1IRQ T0IRQ P01IRQ P00IRQ Read Write R W R W...

Page 59: ...t requests occurs and the program counter PC points to the interrupt vector ORG 8 and the stack add 1 level 0DFH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 STKP GIE STKPB2 STKPB1 STKPB0 Read Writ...

Page 60: ...save and load ACC PFLAG data into buffers and avoid main routine error after interrupt service routine finishing Note PUSH POP instructions save and load ACC PFLAG without NT0 NPD PUSH POP buffer is...

Page 61: ...Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PEDGE P00G1 P00G0 Read Write R W R W After reset 1 0 Bit 4 3 P00G 1 0 P0 0 interrupt trigger edge control bits 00 reserved 01 rising edge 10 falling edge 11 r...

Page 62: ...he P01IRQ is set to be 1 Users need to be cautious with the operation under multi interrupt situation Note The interrupt trigger direction of P0 1 is falling edge Example INT1 interrupt request setup...

Page 63: ...t setup B0BCLR FT0IEN Disable T0 interrupt service B0BCLR FT0ENB Disable T0 timer MOV A 20H B0MOV T0M A Set T0 clock Fcpu 64 MOV A 74H Set T0C initial value 74H B0MOV T0C A Set T0 interval 10 ms B0BSE...

Page 64: ...e TC1 interrupt request setup B0BCLR FTC1IEN Disable TC1 interrupt service B0BCLR FTC1ENB Disable TC1 timer MOV A 20H B0MOV TC1M A Set TC1 clock Fcpu 64 MOV A 74H Set TC1C initial value 74H B0MOV TC1C...

Page 65: ...g IEN and IRQ flags to decide which interrupt to be executed Users have to check interrupt control bit and interrupt request flag in interrupt routine Example Check the interrupt request under multi i...

Page 66: ...it 1 Bit 0 P2M P27M P26M P25M P24M P23M P22M P22M P20M Read Write R W R W R W R W R W R W R W R W After reset 0 0 0 0 0 0 0 0 0C5H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P5M P54M P53M P52M P5...

Page 67: ...W W W After reset 0 0 0 0 0 0 0 0 0E2H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P2UR P27R P26R P25R P24R P23R P22R P21R P20R Read Write W W W W W W W W After reset 0 0 0 0 0 0 0 0 0E5H Bit 7 B...

Page 68: ...2 Bit 1 Bit 0 P1OC P11OC P10OC Read Write W W After reset 0 0 Bit 0 P10OC P10 open drain control bit 0 Disable open drain mode 1 Enable open drain mode Bit 1 P11OC P11 open drain control bit 0 Disable...

Page 69: ...R W R W R W R W R W R W R W After reset 0 0 0 0 0 0 0 0 0D5H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P5 P54 P53 P52 P51 P50 Read Write R W R W R W R W R W After reset 0 0 0 0 0 Note The P02 ke...

Page 70: ...V Watchdog overflow time 8192 Internal Low Speed oscillator sec VDD Internal Low RC Freq Watchdog Overflow Time 3V 16KHz 512ms 5V 32KHz 256ms Note 1 If watchdog is Always_On mode it keeps running even...

Page 71: ...hdog timer is as following To clear the watchdog timer counter in the top of the main routine of the program Main MOV A 5AH Clear the watchdog timer B0MOV WDTR A CALL SUB1 CALL SUB2 JMP MAIN Example C...

Page 72: ...gnal to trigger T0 interrupt to request interrupt service The main purposes of the T0 timer is as following 8 bit programmable up counting timer Generates interrupts at specific time intervals based o...

Page 73: ...D8H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 T0M T0ENB T0rate2 T0rate1 T0rate0 Read Write R W R W R W R W After reset 0 0 0 0 Bit 6 4 T0RATE 2 0 T0 internal clock select bits 000 fcpu 256 001 f...

Page 74: ...0 Fcpu 64 T0C initial value 256 T0 interrupt interval time input clock 256 10ms 4MHz 4 64 256 10 2 4 106 4 64 100 64H The basic timer table interval time of T0 High speed mode Fcpu 4MHz 4 Low speed mo...

Page 75: ...B0BCLR FT0ENB T0 timer B0BCLR FT0IEN T0 interrupt function is disabled B0BCLR FT0IRQ T0 interrupt request flag is cleared Set T0 timer rate MOV A 0xxx0000b The T0 rate control bits exist in bit4 bit6...

Page 76: ...to interrupt vector ORG 8 at next cycle If T0C changing in system operating duration is necessary to disable T0 interrupt function T0IEN 0 before changing T0C value The solution can avoid unexpected...

Page 77: ...l to trigger TC1 interrupt to request interrupt service TC1 overflow time is 0xFF to 0X00 normally Under PWM mode TC1 overflow is still 256 counts The main purposes of the TC1 timer is as following 8...

Page 78: ...ontrol bit Only valid when PWM1OUT 0 0 Disable P5 3 is I O function 1 Enable P5 3 is output TC1OUT signal Bit 2 ALOAD1 Auto reload control bit Only valid when PWM1OUT 0 0 Disable TC1 auto reload funct...

Page 79: ...KS 0 High clock is external 4MHz Fcpu Fosc 4 Select TC1RATE 010 Fcpu 64 TC1C initial value 256 TC1 interrupt interval time input clock 256 10ms 4MHz 4 64 256 10 2 4 106 4 64 100 64H The basic timer ta...

Page 80: ...ock N is TC1 overflow boundary number TC1 timer overflow time has five types TC1 timer TC1 event counter TC1 Fcpu clock source PWM mode and no PWM mode These parameters decide TC1 overflow time and va...

Page 81: ...eform is as following 1 2 3 4 1 2 3 4 TC1 Overflow Clock TC1OUT Buzzer Output Clock Example Setup TC1OUT output from TC1 to TC1OUT P5 3 The external high speed clock is 4MHz The TC1OUT frequency is 0...

Page 82: ...Select TC1 internal external clock source B0BCLR FTC1CKS Select TC1 internal clock source or B0BSET FTC1CKS Select TC1 external clock source Set TC1 timer auto load mode B0BCLR FALOAD1 Enable TC1 aut...

Page 83: ...NOLOGY CO LTD Page 83 Version 1 1 Set TC1 timer function mode B0BSET FTC1IEN Enable TC1 interrupt function or B0BSET FTC1OUT Enable TC1OUT Buzzer function or B0BSET FPWM1OUT Enable PWM function Enable...

Page 84: ...EN Enable TC1 interrupt function and system jumps to interrupt vector ORG 8 at next cycle If TC1C changing in system operating duration is necessary to disable TC1 interrupt function TC1IEN 0 before c...

Page 85: ...n the counter reaches zero the PWM output is forced high The low to high ratio duty of the PWM1 output is TC1R 256 64 32 16 ALOAD1 TC1OUT PWM duty range TC1C valid value TC1R valid bits value MAX PWM...

Page 86: ...DUTY In PWM mode the frequency of TC1IRQ is depended on PWM duty range From following diagram the TC1IRQ frequency is related with PWM duty TC1C Value PWM1 Output Duty Range 0 255 PWM1 Output Duty Ra...

Page 87: ...OV TC1M A Set the TC1 rate to Fcpu 4 MOV A 30 Set the PWM duty to 30 256 B0MOV TC1C A B0MOV TC1R A B0BCLR FTC1OUT Set duty range as 0 256 255 256 B0BCLR FALOAD1 B0BSET FPWM1OUT Enable PWM1 output to P...

Page 88: ...output logic Low If TC1C is changed in certain period the PWM duty will change immediately If TC1R is fixed all the time the PWM waveform is also the same TC1C overflow and TC1IRQ set TC1C TC1R 0xFF...

Page 89: ...outputs correct duty In period 4 the new TC1R value is smaller than the old TC1R value If setting new TC1R is before PWM output low system is getting TC1C TC1R result and making PWM output low In the...

Page 90: ...N XOR A I A A xor I 1 SWAP M A b3 b0 b7 b4 M b7 b4 b3 b0 1 P SWAPM M M b3 b0 b7 b4 M b7 b4 b3 b0 1 N R RRC M A RRC M 1 O RRCM M M RRC M 1 N C RLC M A RLC M 1 E RLCM M M RLC M 1 N S CLR M M 0 1 S BCLR...

Page 91: ...ow Voltage ViL Input with Schmitt trigger Vss 0 2Vdd V Input High Voltage ViH Input with Schmitt trigger 0 8Vdd Vdd V Reset pin leakage current Ilekg Vin Vdd 2 uA Vin Vss Vdd 3V 200 I O port pull up r...

Page 92: ...11 1 2 OTP Writer Writer 3 0 Support SN8P2604 but no Stand alone mode Easy Writer V1 0 OTP programming is controlled by ICE without firmware upgrade suffers Please refer easy writer user manual for de...

Page 93: ...ter code option Enable Noise_Filter can reduce external noise affecting system of operating If Noise_Filter enable the Fcpu is limited in Fosc 4 Fosc 8 11 2 3 WATCHDOG Watchdog of SN8P2604 includes th...

Page 94: ...following ORG 8 CODE ORG 0 0000H JMP START Jump to user program address ORG 8 Interrupt service routine NOP The first instruction at ORG 8 RETI End of interrupt service routine START The head of user...

Page 95: ...It is easy to check the table address from listing file LST after compiling User also can use ORG to set table start address and avoid E6H and E7H Example Set table start address by ORG ORG 0x0100 Se...

Page 96: ...ation ICE_MODE 0 is real chip mode Syntax ICE_MODE Val Val 0 Real chip 1 S8KD 2 ICE emulation Example Setting ICE mode for ICE emulation After compiling the code only supports ICE emulation and can t...

Page 97: ...DD M A 1 B0ADD M A H ADD A I 1 H ADD A I 1 M SBC A M 1 M SBC A M 1 E SBC M A 1 N E SBC M A 1 SBC M A T SUB A M 1 T SUB A M 1 I SUB M A 1 N I SUB M A 1 SUB M A C SUB A I 1 C SUB A I 1 AND A M 1 AND A M...

Page 98: ...user program Example Including SN8P2X_ICE H in user program CHIP SN8P2604 DATA ICE_MODE EQU 0 INCLUDESTD SN8P2X_ICE H SN8P2X_ICE H is a standard macro file and included by INCLUDESTD CODE User program...

Page 99: ...Frequency ICE Fcpu ICE Crystal Frequency Fosc 1 4MHz Fosc 4 16MHz Fosc 2 2MHz Fosc 4 8MHz Fosc 4 1MHz Fosc 4 4MHz Fosc 8 0 5MHz Fosc 4 2MHz Note For different speed crystals modifying ICE HIGH CLK opt...

Page 100: ...timer function correctly Example Reset watchdog timer by setting WDTR as 0x5A CHIP SN8P2604 DATA ICE_MODE EQU 0 INCLUDESTD SN8P2X_ICE H CODE User program MOV A 5Ah Reset watchdog timer B0MOV WDTR A No...

Page 101: ...macros are built in assembler software 11 5 5 1 P00_MODE P01_MODE Syntax P00_MODE Val Val 0 Set P0 0 input mode 1 Set P0 0 output mode Syntax P01_MODE Val Val 0 Set P0 1 input mode 1 Set P0 1 output...

Page 102: ...yntax P00_OUT Val Val 0 Set P0 0 output low 1 Set P0 0 output high Syntax P01_OUT Val Val 0 Set P0 1 output low 1 Set P0 1 output high Example Set P0 0 as output high P00_OUT 1 Example Set P0 0 as out...

Page 103: ...t be 1 for ICE Emulation After ICE emulation set ICE_MODE as 0 and compile again to get SN8 file for real chip Syntax P00_EDGE Val Val 1 Rising edge 2 Falling edge 3 Level change bi direction Example...

Page 104: ...duty setting function SONIX provides PWM Duty setting macro Users can use it to emulate PWM function and don t affect other functions The macro is built in assembler software Users have to set ICE_MOD...

Page 105: ...routines can solve the problem BTS0 BUF 0 JMP CLR_WDT JMP TEST_CODE CLR_WDT RST_WDT TEST_CODE SN8IDE provides user defined forward backward jump directive to processing skipping function easier Macro...

Page 106: ...38 JP2 for Writer V3 0 transition board DIP13 13 36 DIP36 DIP14 14 35 DIP35 DIP15 15 34 DIP34 DIP16 16 33 DIP33 DIP17 17 32 DIP32 DIP18 18 31 DIP31 DIP19 19 30 DIP30 DIP20 20 29 DIP29 DIP21 21 28 DIP2...

Page 107: ...Writer V3 0 Connector OTP IC JP3 Pin Assigment Number Name Number Name Number Pin Number Pin 2 VDD 1 VDD 2 VDD 17 VDD 1 GND 2 GND 4 VSS 18 VSS 4 CLK 3 CLK 6 P5 0 20 P5 0 3 CE 4 CE 6 PGM 5 PGM 10 P1 0...

Page 108: ...1 SK DIP 28 PIN MIN NOR MAX MIN NOR MAX SYMBOLS inch mm A 0 210 5 334 A1 0 015 0 381 A2 0 114 0 130 0 135 2 896 3 302 3 429 D 1 390 1 390 1 400 35 306 35 306 35 560 E 0 310 7 874 E1 0 283 0 288 0 293...

Page 109: ...IN MIN NOR MAX MIN NOR MAX SYMBOLS inch mm A 0 093 0 099 0 104 2 362 2 502 2 642 A1 0 004 0 008 0 012 0 102 0 203 0 305 D 0 697 0 705 0 713 17 704 17 907 18 110 E 0 291 0 295 0 299 7 391 7 493 7 595 H...

Page 110: ...NOR MAX SYMBOLS inch mm A 0 08 2 13 A1 0 00 0 01 0 05 0 25 A2 0 06 0 07 0 07 1 63 1 75 1 88 b 0 01 0 01 0 22 0 38 C 0 00 0 01 0 09 0 20 D 0 39 0 40 0 41 9 90 10 20 10 50 E 0 29 0 31 0 32 7 40 7 80 8 2...

Page 111: ...N MIN NOR MAX MIN NOR MAX SYMBOLS inch mm A 0 210 5 334 A1 0 015 0 381 A2 0 125 0 130 0 135 3 175 3 302 3 429 D 0 980 1 030 1 060 24 892 26 162 26 924 E 0 300 7 620 E1 0 245 0 250 0 255 6 223 6 350 6...

Page 112: ...IN MIN NOR MAX MIN NOR MAX SYMBOLS inch mm A 0 093 0 099 0 104 2 362 2 502 2 642 A1 0 004 0 008 0 012 0 102 0 203 0 305 D 0 496 0 502 0 508 12 598 12 751 12 903 E 0 291 0 295 0 299 7 391 7 493 7 595 H...

Page 113: ...0 0 100 0 150 0 250 A2 0 059 1 500 b 0 008 0 010 0 012 0 200 0 254 0 300 c 0 007 0 008 0 010 0 180 0 203 0 250 D 0 337 0 341 0 344 8 560 8 660 8 740 E 0 228 0 236 0 244 5 800 6 000 6 200 E1 0 150 0 15...

Page 114: ...ay occur Should Buyer purchase or use SONIX products for any such unintended or unauthorized application Buyer shall indemnify and hold SONIX and its officers employees subsidiaries affiliates and dis...

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