SONIX SN32F107, User Manual

Page: 146 / 184

SN32F100 Series
32-Bit Cortex-M0 Micro-Controller
SONiX TECHNOLOGY CO., LTD
Page 146
Version 1.9
Bit Name Description Attribute Reset
31:8 Reserved R 0
7 RXFIFOTHIF
RX FIFO threshold interrupt flag
0: No RX FIFO threshold interrupt
1: RX FIFO threshold triggered.
R 0
6 TXFIFOTHIF
TX FIFO threshold interrupt flag
0: No TX FIFO threshold interrupt
1: TX FIFO threshold triggered.
R 0
5 RXFIFOUDIF
RX FIFO underflow interrupt flag
0: No RX FIFO underflow
1: RX FIFO underflow (RX FIFO is empty and still being read).
R 0
4
TXFIFOOVIF
TX FIFO overflow interrupt flag
0: No TX FIFO overflow
1: TX FIFO overflow (TX FIFO is full and still being written).
R 0
3:0
Reserved R 0
13.6.6 I2S Interrupt Clear register (I2S_IC)
Address Offset: 0x14
Bit Name Description Attribute Reset
31:8 Reserved R 0
7 RXFIFOTHIC
0: No effect
1: Clear RXFIFOTHIF bit
W 0
6 TXFIFOTHIC
0: No effect
1: Clear TXFIFOTHIF bit
W 0
5 RXFIFOUDIC
0: No effect
1: Clear RXFIFOOUDIF bit
W 0
4 TXFIFOOVIC
0: No effect
1: Clear TXFIFOOVIF bit
W 0
3:0
Reserved R 0
13.6.7 I2S RX FIFO register (I2S_RXFIFO)
Address Offset: 0x18
Bit Name Description Attribute Reset
31:0 RXFIFO[31:0]
8 x 32-bit RX FIFO
R 0
13.6.8 I2S TX FIFO register (I2S_TXFIFO)
Address Offset: 0x1C
Bit Name Description Attribute Reset
31:0 TXFIFO[31:0]
8 x 32-bit TX FIFO
W 0
13.7 CODEC ADC REGISTERS
Base Address: 0x4006 4000

Note: Codec ADC Registers are available only when codec mode is selected by I2SMOD=1.
13.7.1 ADC Setting 1 register (ADC_SET1)
Address Offset: 0x540
Bit Name Description Attribute Reset