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SONiX TECHNOLOGY CO. SN8F22711B, User Manual

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SONiX TECHNOLOGY CO. SN8F22711B User Manual Download Page 89

                       SN8F2270B Series 

USB 2.0 Low-Speed 8-Bit Micro-Controller

 

SONiX TECHNOLOGY CO., LTD

                                 

Page 89

                         

 

 

Version 1.3

 

 

0 = Non-suspend status. When MCU wakeup from sleep mode by USB resume wakeup request, the bit will 

changes from 1 to 0 automatically.

 

 

 

1 = Set to 1 by hardware when USB suspend request. 

 

Bit 4

  

BUS_RST:

 USB bus reset. 

 

 

0 = Non-USB bus reset.   

 

 

1 = Set to 1 by hardware when USB bus reset request. 

 

 

9.5.3 USB DATA COUNT REGISTER 

The USB EP0 OUT token data byte counter. 

 

092H 

Bit 7 

Bit 6 

Bit 5 

Bit 4 

Bit 3 

Bit 2 

Bit 1 

Bit 0 

EP0OUT_CNT 

   

UEP0OC4

UEP0OC3

UEP0OC2 UEP0OC1

UEP0OC0

Read/Write 

   

R/W 

R/W 

R/W 

R/W 

R/W 

After 

reset 

   0 0 0 0 0 

 

Bit [4:0]  UEP0C [4:0]: 

USB endpoint 0 OUT token data counter. 

 

9.5.4 USB ENABLE CONTROL REGISTER 

 

The register control the regulator output 3.3 volts enable, SOF packet receive interrupt, NAK handshaking interrupt and 
D- internal 1.5k ohm pull up. 

 

093H 

Bit 7 

Bit 6 

Bit 5 

Bit 4

Bit 3 

Bit 2 

Bit 1 

Bit 0 

USB_INT_EN REG_EN DN_UP_EN 

 

 

 

 

EP2NAK 

_INT_EN 

EP1NAK 

_INT_EN 

Read/Write R/W  R/W 

 

 

 

 

R/W  R/W 

After reset 

1 

0 

 

 

 

 

0 

0 

 

Bit [1:0]

   EPnNAK_INT_EN [1:0]:

 EP1~EP3 NAK transaction interrupts enable control bits

. 

n = 1, 2, 3. 

0 = Disable NAK transaction interrupt request.   

 

 

1 = Enable NAK transaction interrupt request. 

 

Bit 6

 DN_UP_EN:

 D- internal 1.5k ohm pull up resistor control bit. 

0 = Disable D- pull up 1.5k ohm to 3.3volts.   

1 = Enable D- pull up 1.5k ohm to 3.3volts. 

 

Bit 7

 REG_EN:

 3.3volts Regulator control bit. 

0 = Disable regulator output 3.3volts.   

1 = Enable regulator output 3.3volts. This bit must enable when using USB function and I/O port 0, port5. 

 

 

 

Summary of Contents for SN8F22711B

Page 1: ...tended or authorized for us as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the fai...

Page 2: ...ENDMENT HISTORY Version Date Description VER1 0 2009 3 23 version 1 0 VER1 1 2009 6 17 Modify SN8F22721S X K to SN8F22721S X P VER1 2 2009 7 9 Modify PWM output pin to p5 3 VER1 3 2010 3 3 1 Add UE1D...

Page 3: ...E DESCRIPTION 17 2 1 1 4 JUMP TABLE DESCRIPTION 19 2 1 1 5 CHECKSUM CALCULATION 21 2 1 2 CODE OPTION TABLE 22 2 1 3 DATA MEMORY RAM 23 2 1 4 SYSTEM REGISTER 24 2 1 4 1 SYSTEM REGISTER TABLE 24 2 1 4 2...

Page 4: ...et Circuit 46 3 6 5 External Reset IC 46 4 SYSTEM CLOCK 47 4 1 OVERVIEW 47 4 2 CLOCK BLOCK DIAGRAM 47 4 3 OSCM REGISTER 48 4 4 SYSTEM HIGH CLOCK 49 4 4 1 INTERNAL HIGH RC 49 4 5 SYSTEM LOW CLOCK 49 4...

Page 5: ...ION SEQUENCE 75 8 3 TIMER COUNTER 0 TC0 76 8 3 1 OVERVIEW 76 8 3 2 TC0M MODE REGISTER 77 8 3 3 TC0C COUNTING REGISTER 78 8 3 4 TC0R AUTO LOAD REGISTER 79 8 3 5 TC0 CLOCK FREQUENCY OUTPUT BUZZER 80 8 3...

Page 6: ...6 10 2 SIOM MODE REGISTER 99 10 3 SIOB DATA BUFFER 100 10 4 SIOR REGISTER DESCRIPTION 100 11 FLASH 102 11 1 OVERVIEW 102 11 2 FLASH PROGRAMMING ERASE CONTROL REGISTER 103 11 3 PROGRAMMING ERASE ADDRES...

Page 7: ...70B Series USB 2 0 Low Speed 8 Bit Micro Controller SONiX TECHNOLOGY CO LTD Page 7 Version 1 3 17 1 INTRODUCTION 118 17 2 MARKING INDETIFICATION SYSTEM 118 17 3 MARKING EXAMPLE 119 17 4 DATECODE SYSTE...

Page 8: ...al High clock Fosc 6MHz Low Speed USB 2 0 Conforms to USB specification Version 2 0 Four operating modes 3 3V regulator output for USB D pin internal Normal mode Both high and low clocks active 1 5k o...

Page 9: ...e 9 Version 1 3 1 2 SYSTEM BLOCK DIAGRAM INTERRUPT CONTROL ACC Internal Low RC TIMING GENERATOR RAM SYSTEM REGISTERS LVD WATCHDOG TIMER TIMER COUNTER SIO ALU PC FLAGS IR Flash memory Low speed USB SIE...

Page 10: ...2711BS SN8F2271BJ QFN 16 pins VREG33 DN DP VSS 16 15 14 13 VDD 1 12 VREG25 P0 1 INT1 2 11 P1 4 P5 0 SCK 3 F2271BJ 10 P1 6 RST P5 2 SDO 4 9 P1 3 5 6 7 8 P5 1 SDI P1 0 P1 1 P1 2 SN8F22721BP DIP 20 pins...

Page 11: ...e Built wakeup function P1 6 RST I O RST is system external reset input pin under Ext_RST mode Schmitt trigger structure active low and normal stay to high P1 6 Port 1 6 bi direction pin Schmitt trigg...

Page 12: ...ed 8 Bit Micro Controller SONiX TECHNOLOGY CO LTD Page 12 Version 1 3 1 5 PIN CIRCUIT DIAGRAMS Port 0 1 5 structures Pull Up Pin Output Latch PnUR Input Bus PnM Output Bus Pin RST structure Pin Ext Re...

Page 13: ...OCESSOR UNIT CPU 2 1 MEMORY MAP 2 1 1 PROGRAM MEMORY ROM 5K words ROM ROM 0000H Reset vector User reset vector Jump to user start address 0001H 0007H General purpose area 0008H Interrupt vector User i...

Page 14: ...on reset external reset or watchdog timer overflow reset then the chip will restart the program from address 0000h and all system registers will be set as default values It is easy to know reset stat...

Page 15: ...tor The following example shows the way to define the interrupt vector in the program memory Note PUSH POP instructions save and load ACC PFLAG without NT0 NPD PUSH POP buffer is a unique buffer and o...

Page 16: ...of user program User program JMP START End of user program MY_IRQ The head of interrupt service routine PUSH Save ACC and PFLAG register to buffers POP Load ACC and PFLAG register from buffers RETI En...

Page 17: ...TABLE1 L To set lookup table1 s low address MOVC To lookup data R 00H ACC 35H Increment the index address for next address INCMS Z Z 1 JMP F Z is not overflow INCMS Y Z overflow FFH 00 Y Y 1 NOP MOVC...

Page 18: ...To define a word 16 bits data DW 5105H DW 2012H The other example of loop up table is to add Y or Z index register by accumulator Please be careful if carry happen Example Increase Y and Z register by...

Page 19: ...rry after PCL ACC PCH adds one automatically If PCL borrow after PCL ACC PCH keeps value and not change Example Jump table ORG 0X0100 The jump table is from the head of the ROM boundary B0ADD PCL A PC...

Page 20: ...le routine begin from next RAM boundary 0x0100 Example JMP_A operation Before compiling program ROM address B0MOV A BUF0 BUF0 is from 0 to 4 JMP_A 5 The number of the jump table listing is five 0X00FD...

Page 21: ...end address to end_addr2 CLR Y Set Y to 00H CLR Z Set Z to 00H MOVC B0BSET FC Clear C flag ADD DATA1 A Add A to Data1 MOV A R ADC DATA2 A Add R to Data2 JMP END_CHECK Check if the YZ address the end o...

Page 22: ...mode and green mode Watch_Dog Disable Disable Watchdog function Fhosc 1 Instruction cycle is 6 MHz clock Fhosc 2 Instruction cycle is 3 MHz clock Fcpu Fhosc 4 Instruction cycle is 1 5 MHz clock Reset...

Page 23: ...ess RAM location 000h 07Fh General purpose area BANK 0 080h System register BANK 0 0FFh End of bank 0 area 80h FFh of Bank 0 store system registers 128 bytes 100h BANK1 140h General purpose area BANK1...

Page 24: ...egister EP_ACK Endpoint ACK flag register UDR0_W USB FIFO write data buffer by UDP1 point to UToggle USB endpoint toggle bit control register UPID USB bus control register USTATUS USB status register...

Page 25: ...P06 UDP05 UDP04 UDP03 UDP02 UDP01 UDP00 R W UDP0_L 0A4H WE0 RD0 R W UDP0_H 0A5H UDR0_R7 UDR0_R6 UDR0_R5 UDR0_R4 UDR0_R3 UDR0_R2 UDR0_R1 UDR0_R0 R W UDR0_R 0A6H UDR0_W7 UDR0_W6 UDR0_W5 UDR0_W4 UDR0_W3...

Page 26: ...C12 S6PC11 S6PC10 S6PC9 S6PC8 R W STK6H 0F4H S5PC7 S5PC6 S5PC5 S5PC4 S5PC3 S5PC2 S5PC1 S5PC0 R W STK5L 0F5H S5PC12 S5PC11 S5PC10 S5PC9 S5PC8 R W STK5H 0F6H S4PC7 S4PC6 S4PC5 S4PC4 S4PC3 S4PC2 S4PC1 S4...

Page 27: ...n t be access by B0MOV instruction during the instant addressing mode Example Read and write ACC value Read ACC data and store in BUF data memory MOV BUF A Write a immediate data into ACC MOV A 0FH Wr...

Page 28: ...flag NT0 NPD Reset Status 0 0 Watch dog time out 0 1 Reserved 1 0 Reset by LVD 1 1 Reset by external Reset Pin Bit 2 C Carry flag 1 Addition with carry subtraction without borrowing rotation with shif...

Page 29: ...Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PC PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 After reset 0 0 0 0 0 0 0 0 0 0 0 0 0 PCH PCL ONE ADDRESS SKIPPING There ar...

Page 30: ...NCS BUF0 JMP C0STEP Jump to C0STEP if ACC is not zero C0STEP NOP INCMS instruction INCMS BUF0 JMP C0STEP Jump to C0STEP if BUF0 is not zero C0STEP NOP If the destination decreased by 1 which results u...

Page 31: ...alue by the three instructions and don t care PCL overflow problem Note PCH only support PC up counting result and doesn t support PC down counting When PCL is carry after PCL ACC PCH adds one automat...

Page 32: ...W R W R W R W After reset 083H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Z ZBIT7 ZBIT6 ZBIT5 ZBIT4 ZBIT3 ZBIT2 ZBIT1 ZBIT0 Read Write R W R W R W R W R W R W R W R W After reset Example Uses Y Z...

Page 33: ...or store high byte data of look up table MOVC instruction executed the high byte data of specified ROM address will be stored in R register and the low byte data will be stored in ACC 082H Bit 7 Bit 6...

Page 34: ...87 working register 2 2 2 DIRECTLY ADDRESSING MODE The directly addressing mode moves the content of RAM location in or out of ACC Example Move 0x12 RAM location data into ACC B0MOV A 12H To get a con...

Page 35: ...instruction are executed The STKP register is a pointer designed to point active level in order to push or pop up data from stack buffer The STKnH and STKnL are the stack buffers to store program cou...

Page 36: ...service routine Stack operation is a LIFO type Last in and first out The stack pointer STKP and stack buffer STKnH and STKnL are located in the system register area bank 0 0DFH Bit 7 Bit 6 Bit 5 Bit...

Page 37: ...H STK1L 3 1 0 0 STK2H STK2L 4 0 1 1 STK3H STK3L 5 0 1 0 STK4H STK4L 6 0 0 1 STK5H STK5L 7 0 0 0 STK6H STK6L 8 1 1 1 STK7H STK7L 8 1 1 0 Stack Over error There are Stack Restore operations correspond t...

Page 38: ...s cleared After reset status released the system boots up and program starts to execute from ORG 0 The NT0 NPD flags indicate system reset status The system can depend on NT0 NPD status and go to diff...

Page 39: ...llator is not fixed RC type oscillator s start up time is very short but the crystal type is longer Under client terminal application users have to take care the power on reset time for the master ter...

Page 40: ...tchdog timer by program Under error condition system is in unknown situation and watchdog can t be clear by program before watchdog timer overflow Watchdog timer overflow occurs and the system is rese...

Page 41: ...band V1 doesn t touch the below area and not effect the system operation But the V2 and V3 is under the below area and may induce the system error occurrence Let system under dead band includes some c...

Page 42: ...The electrical characteristic section shows the system voltage to executing rate relationship Vdd V System Rate Fcpu System Mini Operating Voltage System Reset Voltage Dead Band Area Normal Operating...

Page 43: ...re detail LVD information is in the electrical characteristic section Watchdog reset The watchdog timer is a protection to make sure the system executes well Normally the watchdog timer would be clear...

Page 44: ...level the system keeps reset status and waits external reset pin released z System initialization All system registers is set as initial conditions and system is ready z Oscillator warm up Oscillator...

Page 45: ...t circuit and Diode RC reset circuit is necessary to limit any current flowing into reset pin from external capacitor C in the event of reset pin breakdown due to Electrostatic Discharge ESD or Electr...

Page 46: ...If the VDD drops and the voltage lower than reset pin detect level the system would be reset If want to make the reset active earlier set the R2 R1 and the cap between VDD and C terminal voltage is l...

Page 47: ...to be the instruction cycle Fcpu Normal Mode High Clock Fcpu Fhosc N N 1 4 Select N by Fcpu code option Slow Mode Low Clock Fcpu Flosc 4 SONIX provides a Noise Filter controlled by code option In high...

Page 48: ...Internal low speed RC oscillator is still running Bit 2 CLKMD System high Low clock mode control bit 0 Normal dual mode System clock is high clock 1 Slow mode System clock is internal low clock Bit 4...

Page 49: ...m In common condition the frequency of the RC oscillator is about 24KHz The internal low RC supports watchdog clock source and system slow mode controlled by CLKMD Flosc Internal low RC oscillator 24K...

Page 50: ...nstruction cycle Fcpu This way is useful in RC mode Example Fcpu instruction cycle of external oscillator B0BSET P0M 0 Set P0 0 to be output mode for outputting Fcpu toggle signal B0BSET P0 0 Output F...

Page 51: ...Bus External Reset Circuit Active System Mode Switching Diagram Operating mode description MODE NORMAL SLOW GREEN POWER DOWN SLEEP REMARK IHRC Running By STPHX By STPHX Stop ILRC Running Running Runni...

Page 52: ...high speed oscillator is still running B0BCLR FCLKMD To set CLKMD 0 Example Switch slow mode to normal mode The external high speed oscillator stops If external high clock stop and program want to sw...

Page 53: ...le T0 timer MOV A 20H B0MOV T0M A To set T0 clock Fcpu 64 MOV A 74H B0MOV T0C A To set T0C initial value 74H To set T0 interval 10 ms B0BCLR FT0IEN To disable T0 interrupt service B0BCLR FT0IRQ To cle...

Page 54: ...WAKEUP TIME When the system is in power down mode sleep mode the high clock oscillator stops When waked up from power down mode MCU waits for 4 internal 6MHz clock or 2048 external 6MHz clocks as the...

Page 55: ...l interrupt can wakeup the chip while the system is switched from power down mode to high speed normal mode Once interrupt service is executed the GIE bit in STKP register will clear to 0 for stopping...

Page 56: ...rol bit 0 Disable WAKEUP interrupt function 1 Enable WAKEUP interrupt function Bit 3 SIOIEN SIO interrupt control bit 0 Disable SIO interrupt function 1 Enable SIO interrupt function Bit 4 T0IEN T0 ti...

Page 57: ...k after the GIE 1 It is necessary for interrupt service request One of the interrupt requests occurs and the program counter PC points to the interrupt vector ORG 8 and the stack add 1 level 0DFH Bit...

Page 58: ...58 Version 1 3 Example Store ACC and PAFLG data by PUSH POP instructions when interrupt service routine executed ORG 0 JMP START ORG 8 JMP INT_SERVICE ORG 10H START INT_SERVICE PUSH Save ACC and PFLAG...

Page 59: ...power down mode or green mode by P0 0 wake up trigger System inserts to interrupt vector ORG 8 after wake up immediately Note INT0 interrupt request can be latched by P0 0 wake up trigger Note INT1 i...

Page 60: ...ervice routine ORG 8 Interrupt vector JMP INT_SERVICE INT_SERVICE Push routine to save ACC and PFLAG to buffers B0BTS1 FP00IRQ Check P00IRQ JMP EXIT_INT P00IRQ 0 exit interrupt vector B0BCLR FP00IRQ R...

Page 61: ...errupt request setup B0BCLR FT0IEN Disable T0 interrupt service B0BCLR FT0ENB Disable T0 timer MOV A 20H B0MOV T0M A Set T0 clock Fcpu 64 MOV A 74H Set T0C initial value 74H B0MOV T0C A Set T0 interva...

Page 62: ...uation Example TC0 interrupt request setup B0BCLR FTC0IEN Disable TC0 interrupt service B0BCLR FTC0ENB Disable TC0 timer MOV A 20H B0MOV TC0M A Set TC0 clock Fcpu 64 MOV A 74H Set TC0C initial value 7...

Page 63: ...Users need to be cautious with the operation under multi interrupt situation Example USB interrupt request setup B0BCLR FUSBIEN Disable USB interrupt service B0BCLR FUSBIRQ Clear USB interrupt request...

Page 64: ...upt vector Users need to be cautious with the operation under multi interrupt situation Example WAKE interrupt request setup B0BCLR FWAKEIEN Disable WAKE interrupt service B0BCLR FWAKEIRQ Clear WAKE i...

Page 65: ...t execute interrupt vector even when the SIOIEN is set to be 1 Users need to be cautious with the operation under multi interrupt situation Example SIO interrupt request setup B0BSET FSIOIEN Enable S...

Page 66: ...executed Users have to check interrupt control bit and interrupt request flag in interrupt routine Example Check the interrupt request under multi interrupt operation ORG 8 Interrupt vector JMP INT_S...

Page 67: ...M P14M P13M P12M P11M P10M Read Write R W R W R W R W R W R W R W After reset 0 0 0 0 0 0 0 0C5H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P5M P53M P52M P51M P50M Read Write R W R W R W R W Afte...

Page 68: ...Write W W W After reset 0 0 0 0E1H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P1UR P16R P15R P14R P13R P12R P11R P10R Read Write W W W W W W W After reset 0 0 0 0 0 0 0 0E5H Bit 7 Bit 6 Bit 5 Bi...

Page 69: ...set 0 0 0 0 0 0 0 0D5H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P5 P53 P52 P51 P50 Read Write R W R W R W R W After reset 0 0 0 0 Note The P1 6 keeps 1 when external reset enable by code option...

Page 70: ...I O PORT1 WAKEUP CONTROL REGISTER 0C0H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P1W P16W P15W P14W P13W P12W P11W P10W Read Write R W R W R W R W R W R W R W After reset 0 0 0 0 0 0 0 Bit 7 0...

Page 71: ...Low Speed oscillator sec VDD Internal Low RC Freq Watchdog Overflow Time 5V 24KHz 341ms Note If watchdog is Always_On mode it keeps running event under power down mode or green mode Watchdog clear is...

Page 72: ...routine fail z Clearing watchdog timer program is only at one part of the program This way is the best structure to enhance the watchdog timer function Example An operation of watchdog timer is as fo...

Page 73: ...sed on the selected clock frequency Green mode wakeup function T0 can be green mode wake up time as T0ENB 1 System will be wake up by T0 time out Fcpu T0 Rate Fcpu 2 Fcpu 256 T0ENB CPUM0 1 T0C 8 Bit B...

Page 74: ...value 256 T0 interrupt interval time input clock Example To set 1ms interval time for T0 interrupt High clock is 6MHz Fcpu Fosc 1 Select T0RATE 010 Fcpu 64 T0C initial value 256 T0 interrupt interval...

Page 75: ...request flag B0BCLR FT0ENB T0 timer B0BCLR FT0IEN T0 interrupt function is disabled B0BCLR FT0IRQ T0 interrupt request flag is cleared Set T0 timer rate MOV A 0xxx0000b The T0 rate control bits exist...

Page 76: ...w time is 0xFF to 0X00 normally Under PWM mode TC0 overflow is decided by PWM cycle controlled by ALOAD0 and TC0OUT bits The main purposes of the TC0 timer is as following 8 bit programmable up counti...

Page 77: ...output control bit Only valid when PWM0OUT 0 0 Disable P5 3 is I O function 1 Enable P5 3 is output TC0OUT signal Bit 2 ALOAD0 Auto reload control bit Only valid when PWM0OUT 0 0 Disable TC0 auto rel...

Page 78: ...256 0x00 0xFF 00000000b 11111111b Overflow per 256 count 1 0 0 256 0x00 0xFF 00000000b 11111111b Overflow per 256 count 1 0 1 64 0x00 0x3F xx000000b xx111111b Overflow per 64 count 1 1 0 32 0x00 0x1F...

Page 79: ...2 TC0R1 TC0R0 Read Write W W W W W W W W After reset 0 0 0 0 0 0 0 0 The equation of TC0R initial value is as following TC0R initial value N TC0 interrupt interval time input clock N is TC0 overflow b...

Page 80: ...2 3 4 TC0 Overflow Clock TC0OUT Buzzer Output Clock Example Setup TC0OUT output from TC0 to TC0OUT P5 3 The external high speed clock is 4MHz The TC0OUT frequency is 0 5KHz Because the TC0OUT signal...

Page 81: ...ource or B0BSET FTC0CKS Select TC0 external clock source Set TC0 timer auto load mode B0BCLR FALOAD0 Enable TC0 auto reload function or B0BSET FALOAD0 Disable TC0 auto reload function Set TC0 interrup...

Page 82: ...to change the PWM s duty cycle is to modify the TC0R Note TC0 is double buffer design Modifying TC0R to change PWM duty by program there is no glitch and error duty signal in PWM output waveform User...

Page 83: ...he TC0IRQ frequency is related with PWM duty TC0 Overflow TC0IRQ 1 PWM0 Output Duty Range 0 15 0xFF TC0C Value 0x00 PWM0 Output Duty Range 0 31 0xFF TC0C Value 0x00 PWM0 Output Duty Range 0 63 0xFF TC...

Page 84: ...n TC0C TC0R PWM output Low If TC0R is changing in the program processing the PWM waveform will became as following diagram 1 1st PWM 2 Update PWM Duty 3 2nd PWM 4 Update PWM Duty 0xFF TC0C Value 0x00...

Page 85: ...0B B0MOV TC0M A Set the TC0 rate to Fcpu 4 MOV A 30 Set the PWM duty to 30 256 B0MOV TC0C A B0MOV TC0R A B0BCLR FTC0OUT Set duty range as 0 256 255 256 B0BCLR FALOAD0 B0BSET FPWM0OUT Enable PWM0 outpu...

Page 86: ...host The hardware handles the following USB bus activity independently of the microcontroller The USB machine will do Translate the encoded received data and format the data to be transmitted on the...

Page 87: ...uence is shown below 1 The host computer sends a SETUP packet followed by a DATA packet to USB address 0 requesting the Device descriptor 2 Firmware decodes the request and retrieves its Device descri...

Page 88: ...9 5 2 USB STATUS REGISTER The USB status register indicates the status of USB 091H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 USTATUS BUS_RST SUSPEND EP0_SETUP EP0_IN EP0_OUT Read Write R R R W...

Page 89: ...ta counter 9 5 4 USB ENABLE CONTROL REGISTER The register control the regulator output 3 3 volts enable SOF packet receive interrupt NAK handshaking interrupt and D internal 1 5k ohm pull up 093H Bit...

Page 90: ...tes with an NAK received 0 the EPnNAK_INT_EN 0 or the endpoint interrupt pipe doesn t complete with an NAK 1 the EPnNAK_INT_EN 1 and the endpoint interrupt pipe complete with an NAK 9 5 7 USB ENDPOINT...

Page 91: ...R W R W R W R W R W R W After reset 0 0 0 0 0 0 0 0 Bit 3 0 UE1C 3 0 Indicate the number of data bytes in a transaction For IN transactions firmware loads the count with the number of bytes to be tran...

Page 92: ...e host from the endpoint 2 FIFO Bit 4 UE2D The IN OUT direction enable bit 0 EP2 only handshake with IN token 1 EP2 only handshake with OUT token Bit 6 5 UE2M 1 0 The endpoint 2 modes determine how th...

Page 93: ...STER 0A5H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 UDR0_R UDR0_R7 UDR0_R6 UDR0_R5 UDR0_R4 UDR0_R3 UDR0_R2 UDR0_R1 UDR0_R0 Read Write R W R W R W R W R W R W R W R W After reset 0 0 0 0 0 0 0 0...

Page 94: ...R W R W R W After reset 0 0 0 0 0 Bit 0 DDN Drive D on the USB bus 0 drive D low 1 drive D high Bit 1 DDP drive D on the USB bus 0 drive D low 1 drive D high Bit 2 UBDE Enable to direct drive USB bus...

Page 95: ...sable EP0 IN STALL function 1 Enable EP0 IN STALL function If this function is enable EP0 IN token always handshakes STALL The EP0 OUT token handshakes depend on UE0R This flag will clear at next SETU...

Page 96: ...2 is programmable open drain output pin for multiple salve devices application z Two programmable bit rates Only in master mode z End of Transfer interrupt The SIOM register can control SIO operating...

Page 97: ...efore the next byte has been completely shifted in Otherwise the first byte is lost Following figure shows a typical SIO transfer between two SN8F2270B micro controllers Master MCU sends SCK for initi...

Page 98: ...ler SONiX TECHNOLOGY CO LTD Page 98 Version 1 3 The SIO data transfer timing as following figure M L S B C P O L C P H A SCK Idle Status Diagrams 0 0 1 Low 0 1 1 High 0 0 0 Low 0 1 0 High 1 0 1 Low 1...

Page 99: ...lock Phase bit controls the phase of the clock on which data is sampled 0 Data receive at the fisrt clock phase 1 Data receive at the second clock phase Note 1 If SCKMD 1 for external clock the SIO is...

Page 100: ...t 1 Bit 0 SIOR R7 SIOR6 SIOR5 SIOR4 SIOR3 SIOR2 SIOR1 SIOR0 SIO Read W W W W W W W W rite W After res 0 0 0 0 0 0 0 et 0 he SIOR is designed for the SIO counter to reload the counted value when end of...

Page 101: ...0 FSTART Wait the end of SIO operation JMP CHK_END B0MOV A SIOB Save SIOB data into RXDATA buffer MO XDATA Load transfe into SI gister B0MOV A MOV 100001 Setup SIOM and enable SIO function B0MOV IOM A...

Page 102: ...e option R erased from tion cod code opt Watch dog timer should be clear before the Flash write or erase operation The erase operation sets all the bits in the Flash page to logic 1 Hardware will hold...

Page 103: ...Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PEROMH PEROMH7 PEROMH6 PEROMH5 PEROMH4 PEROMH3 PEROMH2 PEROMH1 PEROMH0 Read Write R W R W R W R W R W R W R W R W After reset 0 0 0 0 0 0 0 0 Bit 7 0 PEROMH 7 0 Def...

Page 104: ...0H 0011H General purpose area 1380H 13FBH End of user program 13FCH 13FDH 13FEH 13FFH SECURITY0 protect Reserved Code option Flash ROM mapping Note 1 If the code option SECURITY0 1 SECURITY enable the...

Page 105: ...The valid RAM addresses are 00H 07FH PERAMCNT 7 3 Defines the number of words wanted to be programmed The maximum PERAMCNT 7 3 is 01FH which program 32 words RAM to the Flash The minimum PERAM ich pro...

Page 106: ...or M 1 XOR M A M A xor M 1 N X 1 OR A I A A xor I SWAP M A b3 b0 b7 b4 M b7 b4 b3 b0 1 P SWAPM M M b3 b0 b7 b4 M b7 b4 b3 b0 1 N R RRC M A RRC M 1 O RRCM M M RRC M 1 N C RLC M A RLC M 1 E RLCM M M RLC...

Page 107: ...des ICE in circuit emulation IDE Integ opment Environment EV kit and r a li or US tion devel t ICE and EV kit are external hardware device and IDE is a friend u r i for fi a elop t ulation 1 E n t Emu...

Page 108: ...of SN8F2270B EV kit is as following 8F2270B EV kit d VREG 3 3V power supply z CON2 ICE Interface Interface connected to SN8ICE2K_FSUSB_V2 1 z J2 Jumper to connect between the 5V VDD from SN8ICE2K Plu...

Page 109: ...TECHNOLOGY CO LTD Page 109 Version 1 3 13 3 SN8F2270B Transition Board both C1 and C2 MUST be welded by 1uF capacitor SN8F2270B Transition Boards includes total 2 models The following shows the transi...

Page 110: ...REG 0 3 V 33 Voh1 P1 P5 3 output ports 0 Vdd V Output Voltage Voh2 P0 P5 0 P5 1 P5 2 output ports 0 VREG33 V Reset pin leakage current Ilekg Vin Vdd 2 uA I O port pull up resistor Rup1 Rup1 P1 P5 3 s...

Page 111: ...oading Fcpu Fosc 1 Vdd 5V 6Mhz 4 6 mA Idd2 Slow Mode Vdd 5V 24Khz 190 250 uA Internal low RC Idd3 Sleep Mode Vdd 5V 190 250 uA Vdd 5V 6Mhz 1 2 mA Supply Current Idd4 Green Mode No loading Fcpu Fosc 4...

Page 112: ...h IC JP3 Pin Assigment Numbe r b Pin n r Num r Number Name Num er Number Pi Numbe Pin be Pin Pin 1 VDD 1 VDD 18 VDD 3 VDD 2 GND 13 VSS 14 VSS 13 VSS 3 CLK 8 P1 2 8 P1 2 8 P1 2 4 CE 5 PGM 6 P1 0 6 P1 0...

Page 113: ...IN NOR MAX SYMBOLS inch mm A 0 058 0 064 0 068 1 4732 1 6256 1 7272 A1 0 004 0 010 0 1016 0 254 B 0 013 0 016 0 020 0 3302 0 4064 0 508 C 0 0075 0 008 0 0098 0 1905 0 2032 0 2490 D 0 336 0 341 0 344 8...

Page 114: ...16 2 SOP 20 PIN MIN NOR MAX MIN NOR MAX SYMBOLS inch mm A 0 093 0 099 0 104 2 362 2 502 2 642 A1 0 004 0 008 0 012 0 102 0 203 0 305 D 0 496 0 502 0 508 12 598 12 751 12 903 E 0 291 0 295 0 299 7 391...

Page 115: ...04 0 010 0 100 0 250 0 006 0 150 A2 0 059 1 500 b 0 008 0 010 0 012 0 200 0 254 0 300 c 0 007 0 008 0 010 0 180 0 203 0 250 D 0 337 0 341 0 344 8 560 8 660 8 740 E 0 228 0 236 0 244 5 800 6 000 6 200...

Page 116: ...4 P DIP 20 PIN MIN NOR MAX MIN NOR MAX SYMBOLS inch mm A 0 210 5 334 A1 0 015 0 381 A2 0 125 0 130 0 135 3 175 3 302 3 429 D 0 980 1 060 24 892 26 924 1 030 26 162 E 0 300 7 620 E1 0 245 0 250 0 255 6...

Page 117: ...SN8F2270B Series USB 2 0 Low Speed 8 Bit Micro Controller SONiX TECHNOLOGY CO LTD Page 117 Version 1 3 16 5 QFN 16 PIN...

Page 118: ...oduction line This note listed the production definition of all 8 bit MCU for order or obtain information 17 2 MARKING INDETIFICATION SYSTEM Title SONiX 8 bit MCU Production ROM Type P OTP Material B...

Page 119: ...SSOP 0 70 PB Free Package SN8F22721BPG Flash memory 22721B P DIP 0 70 Green Package SN8F22721BSG Flash memory 22721B SOP 0 70 Green Package SN8F22721BXG Flash memory 22721B SSOP 0 70 Green Package F22...

Page 120: ...death may occur Should Buyer purchase or use SONIX products for any such unintended or unauthorized application Buyer shall indemnify and hold SONIX and its officers employees subsidiaries affiliates...

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