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Small Footprint Hi-Speed USB 2.0 Device PHY with UTMI Interface

Datasheet

SMSC USB3290

31

Revision 1.5 (11-02-07)

DATASHEET

8.6

Suspend Detection

If a HS device detects SE0 asserted on the bus for more than 3ms (T1), it reverts to FS mode.  This
enables the FS pull-up on the DP line in an attempt to assert a continuous FS J state on the bus.  The
SIE must then check LINESTATE for the J condition.  If J is asserted at time T2, then the upstream
port is asserting a soft SE0 and the USB is in a J state indicating a suspend condition.  By time T4
the device must be fully suspended.

Figure 8.2 Suspend Timing Behavior (HS Mode)

Table 8.5 Suspend Timing Values (HS Mode)

TIMING

PARAMETER

DESCRIPTION

VALUE

HS Reset T0

End of last bus activity, signaling either a reset
or a SUSPEND.

0 (reference)

T1

The time at which the device must place itself
in FS mode after bus activity stops.

HS Reset T0 + 3. 0ms < T1 < HS Reset T0
+ 3.125ms

T2

SIE samples LINESTATE. If LINESTATE = 'J',
then the initial SE0 on the bus (T0 - T1) had
been due to a Suspend state and the SIE
remains in HS mode.

T1 + 100 µs < T2 <
T1 + 875µs

T3

The earliest time where a device can issue
Resume signaling.

HS Reset T0 + 5ms

T4

The latest time that a device must actually be
suspended, drawing no more than the
suspend current from the bus.

HS Reset T0 + 10ms

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Summary of Contents for USB3290

Page 1: ...D 78 Class II ESD protection levels of 5kV HBM without external protection devices SYNC and EOP generation on transmit packets and detection on receive packets NRZI encoding and decoding Bit stuffing and unstuffing with error detection Supports the USB suspend state HS detection HS Chirp Reset and Resume Support for all test modes defined in the USB 2 0 specification 55mA Unconfigured Current typi...

Page 2: ...e product may contain design defects or errors known as anomalies which may cause the product s functions to deviate from published specifications Anomaly sheets are available upon request SMSC products are not designed intended authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe property damage Any a...

Page 3: ... Circuit 22 7 4 TX Logic 22 7 5 RX Logic 23 7 6 USB 2 0 Transceiver 26 7 6 1 High Speed and Full Speed Transceivers 26 7 6 2 Termination Resistors 26 7 6 3 Bias Generator 27 7 7 Crystal Oscillator and PLL 27 7 8 Internal Regulators and POR 27 7 8 1 Internal Regulators 27 7 8 2 Power On Reset POR 27 7 8 3 Reset Pin 27 Chapter 8 Application Notes 28 8 1 Linestate 28 8 2 OPMODES 29 8 3 Test Mode Supp...

Page 4: ...stuffed Bits 23 Figure 7 5 Receive Timing for a Handshake Packet no CRC 24 Figure 7 6 Receive Timing for Setup Packet 25 Figure 7 7 Receive Timing for Data Packet with CRC 16 25 Figure 8 1 Reset Timing Behavior HS Mode 30 Figure 8 2 Suspend Timing Behavior HS Mode 31 Figure 8 3 HS Detection Handshake Timing Behavior FS Mode 33 Figure 8 4 Chirp K J K J K J Sequence Detection State Diagram 34 Figure...

Page 5: ...6 2 DC Electrical Characteristics Logic Pins Note 6 2 13 Table 6 3 DC Electrical Characteristics Analog I O Pins DP DM Note 6 3 14 Table 6 4 Dynamic Characteristics Analog I O Pins DP DM Note 6 4 15 Table 6 5 Dynamic Characteristics Digital UTMI Pins Note 6 5 16 Table 7 1 DP DM Termination vs Signaling Mode 26 Table 8 1 Linestate States 28 Table 8 2 Operational Modes 29 Table 8 3 USB 2 0 Test Mode...

Page 6: ...sipation which is ideal for building a bus powered USB 2 0 peripheral The PHY uses an 8 bit bidirectional parallel interface which complies with the USB Transceiver Macrocell Interface UTMI specification It supports 480Mbps transfer rate while remaining backward compatible with USB 1 1 legacy protocol at 12Mbps All required termination and 5 25V short circuit protection of the DP DM lines are inte...

Page 7: ...OGIC Clock Recovery Unit Clock and Data Recovery Elasticity Buffer VP VM BIASING Bandgap Voltage Reference Current Reference RBIAS VDD3 3 PLL and XTAL OSC System Clocking FS RX FS SE HS RX HS SQ RX State Machine Serial to Parallel Conversion Bit Unstuff NRZI Decode RX LOGIC DM TX 1 5kΩ FS TX HS TX HS_DATA HS_CS_ENABLE HS_DRIVE_ENABLE OEB VMO VPO RPU_EN MUX DP RXVALID RXACTIVE RXERROR TXREADY RESET...

Page 8: ...ion 1 5 11 02 07 8 SMSC USB3290 DATASHEET Chapter 3 Pinout Figure 3 1 USB3290 Pinout Top View TOP VIEW TSEL TXR SPDN TXV RST V33 V33 DP XSEL GND CLK DM V33 RXA OM0 LS1 LS0 OM1 D6 D7 RXV D0 D5 D2 D3 D4 D1 RB VIO V18A XI XO V18 V33 RXE REN G E C B A F D 1 7 6 5 4 3 2 GND GND GND VIO ...

Page 9: ...wn all blocks not necessary for Suspend Resume operation While suspended TERMSELECT must always be in FS mode to ensure that the 1 5kΩ pull up on DP remains powered 0 Transceiver circuitry drawing suspend current 1 Transceiver circuitry drawing normal current CLKOUT CLK Output Rising Edge System Clock This output is used for clocking receive and transmit parallel data at 60MHz OPMODE 1 0 OM1 OM0 I...

Page 10: ...he data from the bus and is ready for the next transfer on the bus If TXVALID is negated TXREADY can be ignored by the SIE RXVALID RXV Output High Receive Data Valid Indicates that the DATA bus has received valid data The Receive Data Holding Register is full and ready to be unloaded The SIE is expected to latch the DATA bus on the rising edge of CLKOUT RXACTIVE RXA Output High Receive Active Indi...

Page 11: ...nd a bypass capacitor 0 1μF recommended should be connected to each pin The voltage at VDD3 3 must be at least 2 64V 0 8 3 3V before voltage is applied to VDDA1 8 and VDD1 8 VDD1 8 V18 N A N A 1 8V Digital Supply Supplied by On Chip Regulator when REG_EN is active Low ESR 4 7uF minimum capacitor requirement when using internal regulators Do not connect VDD1 8 to VDDA1 8 when using internal regulat...

Page 12: ... Storage Temperature TSTG 55 150 o C ESD PERFORMANCE All Pins VHBM Human Body Model 5 kV LATCH UP PERFORMANCE All Pins ILTCH_UP EIA JESD 78 Class II 150 mA Table 5 2 Recommended Operating Conditions PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 3 3V Supply Voltage VDD3 3 and VDDA3 3 VDD3 3 3 0 3 3 3 6 V Input Voltage on Digital Pins VI 0 0 VDD3 3 V Input Voltage on Analog I O Pins DP DM VI I O 0 0...

Page 13: ...ent IAVG FSTX FS current during data transmit 60 5 mA FS Receive Current IAVG FSRX FS current during data receive 57 5 mA HS Idle Current IAVG HS HS idle not data transfer 60 6 mA HS Transmit Current IAVG HSTX HS current during data transmit 62 4 mA HS Receive Current IAVG HSRX HS current during data receive 61 5 mA Low Power Mode IDD LPM VBUS 15kΩ pull down and 1 5kΩ pull up resistor currents not...

Page 14: ...esistor on DP RL 1 5kΩ to VDD3 3 0 3 V High Level Output Voltage VFSOH Pull down resistor on DP DM RL 15kΩ to GND 2 8 3 6 V Termination Driver Output Impedance for HS and FS ZHSDRV Steady state drive See Figure 6 1 40 5 45 49 5 Ω Input Impedance ZINP TX RPU disabled 10 MΩ Pull up Resistor Impedance ZPU Bus Idle 0 900 1 24 1 575 kΩ Pull up Resistor Impedance ZPURX Device Receiving 1 425 2 26 3 09 k...

Page 15: ...CIN Pin to GND 5 10 pF Table 6 4 Dynamic Characteristics Analog I O Pins DP DM Note 6 4 PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS FS Output Driver Timing Rise Time TFSR CL 50pF 10 to 90 of VOH VOL 4 20 ns Fall Time TFFF CL 50pF 10 to 90 of VOH VOL 4 20 ns Output Signal Crossover Voltage VCRS Excluding the first transition from IDLE state 1 3 2 0 V Differential Rise Fall Time Matching FRFM Excl...

Page 16: ...V I curve for the driver must fall entirely inside the shaded region The V I region is bounded by the minimum driver impedance above 40 5 Ohm and the maximum driver impedance below 49 5 Ohm The output voltage must be within 10mV of ground when no current is flowing in or out of the pin Table 6 5 Dynamic Characteristics Digital UTMI Pins Note 6 5 PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS UTMI T...

Page 17: ...cteristics for High speed Capable Transceiver Figure 6 2 Full Speed Driver VOL IOL Characteristics for High speed Capable Transceiver Vout Volts VOH 0 0 Drive High 0 698 VOH Test Limit Slope 1 49 5 Ohm Slope 1 40 5 Ohm 0 566 VOH 10 71 VOH 6 1 VOH Iout mA Vout Volts VOH 0 0 Drive Low Iout mA 22 1 09V 0 434 VOH Test Limit Slope 1 40 5 Ohm Slope 1 49 5 Ohm 10 71 VOH ...

Page 18: ...ye patterns For measuring the eye patterns 4 points have been defined see Figure 6 3 The Universal Serial Bus Specification Rev 2 0 defines the eye patterns in several templates The two templates that are relevant to the PHY are shown below Figure 6 3 Eye Pattern Measurement Planes USB Cable Transceiver Device Circuit Board Transceiver Hub Circuit Board Connector Traces Traces A Connector B TP1 TP...

Page 19: ...he unit interval UI which represents the nominal bit duration for a 480 Mbit s transmission rate Figure 6 4 Eye Pattern for Transmit Waveform and Eye Pattern Definition VOLTAGE LEVEL D D TIME OF UNIT INTERVAL Level 1 525mV in UI following a transition 475mV in all others N A Level 2 525mV in UI following a transition 475mV in all others N A Point 1 0V 7 5 UI Point 2 0V 92 5 UI Point 3 300mV 37 5 U...

Page 20: ...ls and timings are given in the table below Timings are given as a percentage of the unit interval UI which represents the nominal bit duration for a 480 Mbit s transmission rate Figure 6 5 Eye Pattern for Receive Waveform and Eye Pattern Definition VOLTAGE LEVEL D D TIME OF UNIT INTERVAL Level 1 575mV N A Level 2 575mV N A Point 1 0V 15 UI Point 2 0V 85 UI Point 3 150mV 35 UI Point 4 150mV 65 UI ...

Page 21: ...ed to the CLKOUT output The behavior of the CLKOUT is as follows Produce the first CLKOUT transition no later than 5 6ms after negation of SUSPENDN The CLKOUT signal frequency error is less than 10 at this time The CLKOUT signal will fully meet the required accuracy of 500ppm no later than 1 4ms after the first transition of CLKOUT In HS mode there is one CLKOUT cycle per byte time The frequency o...

Page 22: ...very Circuit This block consists of the Clock and Data Recovery Circuit and the Elasticity Buffer The Elasticity Buffer is used to compensate for differences between the transmitting and receiving clock domains The USB 2 0 specification defines a maximum clock error of 1000ppm of drift 7 4 TX Logic This block receives parallel data bytes placed on the DATA bus and performs the necessary transmit o...

Page 23: ...The processing involved includes NRZI decoding bit unstuffing and serial to parallel conversion Upon valid assertion of the proper RX control lines by the RX State Machine the RX Logic block will provide bytes to the DATA bus as shown in the figures below The behavior of the Receive State Machine is described below The assertion of RESET will force the Receive State Machine into the Reset state Th...

Page 24: ...us byte time This will occur if 8 stuffed bits have been accumulated The SIE must be ready to consume a data byte if RXACTIVE and RXVALID are asserted RX Data state Figure 7 5 shows the timing relationship between the received data DP DM RXVALID RXACTIVE RXERROR and DATA signals Notes The USB 2 0 Transceiver does NOT decode Packet ID s PIDs They are passed to the SIE for decoding Figure 7 5 Figure...

Page 25: ...de the selected receiver provides the serial data stream through the mulitplexer to the RX Logic block The FS mode section of the FS HS RX block also consists of a single ended receiver on each of the data lines to determine the correct FS LINESTATE For HS mode support the FS HS RX block contains a squelch circuit to insure that noise is never interpreted as data Figure 7 6 Receive Timing for Setu...

Page 26: ...he block contains a separate differential FS and HS transmitter which receive encoded bit stuffed serialized data from the TX Logic block and transmit it on the USB cable 7 6 2 Termination Resistors The USB3290 transceiver fully integrates all of the USB termination resistors The USB3290 includes the 1 5kΩ pull up resistor on DP In addition the 45Ω high speed termination resistors are also integra...

Page 27: ...wer management features include a POR generation and allow the USB3290 to be powered from a single 3 3 volt power supply This reduces the bill of materials and simplifies product design 7 8 1 Internal Regulators The USB3290 has two integrated 3 3 volt to 1 8 volt regulators These regulators require an external 4 7uF 20 low ESR bypass capacitor to ensure stability X5R or X7R ceramic capacitors are ...

Page 28: ...e single ended thresholds in the USB 2 0 specification for HS mode The HS receiver is used to detect Chirp J or K where the output of the HS receiver is always qualified with the Squelch signal If squelched the output of the HS receiver is ignored In the USB3290 as an alternative to using variable thresholds for the single ended receivers the following approach is used In HS mode 3ms of no USB act...

Page 29: ... transmitting or receiving data will generate undefined results Under no circumstances should the device controller change OPMODE while the DP DM lines are still transmitting or unpredictable changes on DP DM are likely to occur The same applies for TERMSELECT and XCVRSELECT 8 3 Test Mode Support Table 8 2 Operational Modes MODE 1 0 STATE STATE NAME DESCRIPTION 00 0 Normal Operation Transceiver op...

Page 30: ...ation is made If a reset is signaled the HS device will then initiate the HS Detection Handshake protocol 8 5 Reset Detection If a device in HS mode detects bus inactivity for more than 3ms T1 it reverts to FS mode This enables the FS pull up on the DP line in an attempt to assert a continuous FS J state on the bus The SIE must then check LINESTATE for the SE0 condition If SE0 is asserted at time ...

Page 31: ...he device must be fully suspended Figure 8 2 Suspend Timing Behavior HS Mode Table 8 5 Suspend Timing Values HS Mode TIMING PARAMETER DESCRIPTION VALUE HS Reset T0 End of last bus activity signaling either a reset or a SUSPEND 0 reference T1 The time at which the device must place itself in FS mode after bus activity stops HS Reset T0 3 0ms T1 HS Reset T0 3 125ms T2 SIE samples LINESTATE If LINEST...

Page 32: ... If an SE0 state is detected then the device will enter the HS Handshake detection process In each case the assertion of the SE0 state on the bus initiates the reset The minimum reset interval is 10ms Depending on the previous mode that the bus was in the delay between the initial assertion of the SE0 state and entering the HS Handshake detection can be from 0 to 4ms This transceiver design pushes...

Page 33: ...ING PARAMETER DESCRIPTION VALUE T0 HS Handshake begins DP pull up enabled HS terminations disabled 0 reference T1 Device enables HS Transceiver and asserts Chirp K on the bus T0 T1 HS Reset T0 6 0ms T2 Device removes Chirp K from the bus 1ms minimum width T1 1 0 ms T2 HS Reset T0 7 0ms T3 Earliest time when downstream facing port may assert Chirp KJ sequence on the bus T2 T3 T2 100µs T4 Chirp not ...

Page 34: ...S mode by setting TERMSELECT to HS mode T7 Figure 8 4 provides a state diagram for Chirp K J K J K J validation Prior to the end of reset T9 the device port must terminate the sequence of Chirp K s and Chirp J s T8 and assert SE0 T8 T9 Note that the sequence of Chirp K s and Chirp J s constitutes bus activity The Chirp K J K J K J sequence occurs too slow to propagate through the serial data path ...

Page 35: ...cing port asserts Chirp K on the bus T2 T3 T2 100µs T4 Downstream facing port toggles Chirp K to Chirp J on the bus T3 40µs T4 T3 60µs T5 Downstream facing port toggles Chirp J to Chirp K on the bus T4 40µs T5 T4 60µs T6 Device detects downstream port chirp T6 T7 Chirp detected by the device Device removes DP pull up and asserts HS terminations reverts to HS default state and waits for end of rese...

Page 36: ...y negated at time T0 by the SIE It takes approximately 5 milliseconds for the transceiver s oscillator to stabilize The device does not generate any transitions of the CLKOUT signal until it is usable where usable is defined as stable to within 10 of the nominal frequency and the duty cycle accuracy 50 5 The first transition of CLKOUT occurs at T1 The SIE then sets OPMODE to Disable Bit Stuffing a...

Page 37: ...in suspend state an SE0 is detected on the USB HS Handshake begins D pull up enabled HS terminations disabled SUSPENDN negated 0 HS Reset T0 T1 First transition of CLKOUT CLKOUT Usable frequency accurate to 10 duty cycle accurate to 50 5 T0 T1 T0 5 6ms T2 Device asserts Chirp K on the bus T1 T2 T0 5 8ms T3 Device removes Chirp K from the bus 1 ms minimum width and begins looking for host chirps T2...

Page 38: ... HS mode after being suspended At T4 a device that was previously in FS mode would maintain TERMSELECT and XCVRSELECT high To generate resume signaling FS K the device is placed in the Disable Bit Stuffing and NRZI encoding Operational Mode OPMODE 1 0 10 TERMSELECT and XCVRSELECT must be in FS mode TXVALID asserted and all 0 s data is presented on the DATA bus for at least 1ms T1 T2 Figure 8 7 Res...

Page 39: ...s the FS terminations enabled After the SE0 expires the downstream port will assert a J state for one low speed bit time and the bus will enter a FS Idle state maintained by the FS terminations If the device was in HS mode then the SIE must switch to the FS terminations before the SE0 expires 1 25µs After the SE0 expires the bus will then enter a HS IDLE state maintained by the HS terminations 8 1...

Page 40: ... Figure 8 8 Device Attach Behavior Table 8 10 Attach and Reset Timing Values TIMING PARAMETER DESCRIPTION VALUE T0 Vbus Valid 0 reference T1 Maximum time from Vbus valid to when the device must signal attach T0 100ms T1 T2 HS Reset T0 Debounce interval The device now enters the HS Detection Handshake protocol T1 100ms T2 ...

Page 41: ...tion Diagram showing USB related signals Opmode 0 Opmode 1 Xcvrselect 0 Termselect SuspendM Reset Txvalid Rxvalid Rxerror Rxactive Linestate 1 Linestate 0 Txready Clkout USB3290 Data0 DP DM DP DM VBUS Optional Level Shifter USB Connector B Data1 Data2 Data3 Data4 Data5 Data6 Data7 G3 F4 B1 C2 D1 E2 D2 C1 A7 F3 A6 F5 B7 C7 D6 D7 E6 E7 F7 G7 F1 E1 G5 G4 To VBUS detect input ...

Page 42: ... DATASHEET Figure 8 10 USB3290 Application Diagram showing power and miscellaneous signals 1M 3 3 Volt Supply B5 4 7uF 0 1uF USB3290 VDDIO G6 VDDIO VDDA18 C6 VDD18 B3 VDD33 G1 VDD33 G2 VDD33 A5 VDD33 B2 GND B6 GND F2 GND A2 REG_EN B4 4 7uF 0 1uF 12 0k A1 RBIAS 30pF 30pF 24 MHz XTAL A3 XI A4 XO 4 7uF 0 1uF F6 GND ...

Page 43: ... USB 2 0 Device PHY with UTMI Interface Datasheet Revision 1 5 11 02 07 43 SMSC USB3290 DATASHEET Chapter 9 Package Outline Figure 9 1 USB3290 FH 40 Ball VFBGA Package Outline Parameters 4x4x0 9mm Body Lead Free RoHS Compliant ...

Page 44: ...Small Footprint Hi Speed USB 2 0 Device PHY with UTMI Interface Datasheet Revision 1 5 11 02 07 44 SMSC USB3290 DATASHEET Figure 9 2 BGA 4x4 Taping Dimensions and Part Orientation ...

Page 45: ...Small Footprint Hi Speed USB 2 0 Device PHY with UTMI Interface Datasheet SMSC USB3290 45 Revision 1 5 11 02 07 DATASHEET Figure 9 3 Reel Dimensions for 12mm Carrier Tape ...

Page 46: ...l Footprint Hi Speed USB 2 0 Device PHY with UTMI Interface Datasheet Revision 1 5 11 02 07 46 SMSC USB3290 DATASHEET Note Standard reel size is 4000 pieces per reel Figure 9 4 Tape Length and Part Quantity ...

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