Small Footprint Hi-Speed USB 2.0 Device PHY with UTMI Interface
Datasheet
Revision 1.5 (11-02-07)
24
SMSC USB3290
DATASHEET
When the EOP is detected the state machine will enter the
Strip EOP
state and negate RXACTIVE
and RXVALID. After the EOP has been stripped the Receive State Machine will reenter the
RX Wait
state and begin looking for the next packet.
The behavior of the Receive State Machine is described below:
RXACTIVE and RXREADY are sampled on the rising edge of CLKOUT.
In the RX Wait state the receiver is always looking for SYNC.
The USB3290 asserts RXACTIVE when SYNC is detected (Strip SYNC state).
The USB3290 negates RXACTIVE when an EOP is detected and the elasticity buffer is empty
(Strip EOP state).
When RXACTIVE is asserted, RXVALID will be asserted if the RX Holding Register is full.
RXVALID will be negated if the RX Holding Register was not loaded during the previous byte time.
This will occur if 8 stuffed bits have been accumulated.
The SIE must be ready to consume a data byte if RXACTIVE and RXVALID are asserted (RX Data
state).
shows the timing relationship between the received data (DP/DM), RXVALID,
RXACTIVE, RXERROR and DATA signals.
Notes:
The USB 2.0 Transceiver does NOT decode Packet ID's (PIDs). They are passed to the SIE for
decoding.
and
are timing examples of a HS/FS PHY when it is in HS mode.
When a HS/FS PHY is in FS Mode there are approximately 40 CLKOUT cycles every byte time.
The Receive State Machine assumes that the SIE captures the data on the DATA bus if RXACTIVE
and RXVALID are asserted. In FS mode, RXVALID will only be asserted for one CLKOUT per byte
time.
In
the SYNC pattern on DP/DM is shown as one byte long.
The SYNC pattern received by a device can vary in length. These figures assume that all but the
last 12 bits have been consumed by the hubs between the device and the host controller.
Figure 7.5 Receive Timing for a Handshake Packet (no CRC)
