Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface
Datasheet
SMSC LAN9420/LAN9420i
81
Revision 1.22 (09-25-08)
DATASHEET
Two control bits are implemented in the PMT_CTRL SCSR: Wake-on-LAN enable (WOL_EN) and
Energy Detect enable (ED_EN). Depending on the state of these control bits, the logic will generate
an internal wake event interrupt when the MAC detects a wakeup event (Wakeup Frame or Magic
Packet), or a PHY interrupt is asserted (energy detect). Two
are implemented
in the SCSR space. These bits are set depending on the corresponding wake event. (See
4.2.9, "Power Management Control Register (PMT_CTRL)," on page 97
for further information)
Wakeup Frame detection must be enabled in the MAC before detection can occur. Likewise, the
energy detect interrupt must be enabled in the PHY before this interrupt can be used as a wake event.
If LAN9420/LAN9420i is properly configured, the internal wake event interrupt will cause the assertion
of the nPME signal on detection of a wake event.
When the device is in the D0
A
state, wake event detection can also trigger the assertion of a PCI
interrupt (nINT). Upon detection of the wake event, the wake logic sets the
status bit in the
Interrupt Status Register (INT_STS)
. If so enabled, setting this status bit
will cause the assertion of nINT.
3.7.6.1
Enabling Wakeup Frame Wake Events
The Host system must perform the following steps to enable LAN9420/LAN9420i to assert a PCI wake
event (nPME) on detection of a Wakeup frame.
1. All transmit and receive operations must be halted:
a. All pending Ethernet TX and RX operations must be completed, and then the DMA controller and
MAC must be halted.
b. The software application must wait for all pending DMA transactions to complete. Upon completion,
no further transactions are permitted.
2. The MAC must be configured to detect the desired wake event. This process is explained in
Section 3.5.4, "Wakeup Frame Detection," on page 57
.
3. Bit 1 of the Wakeup Status (WUPS[1]) in the
Power Management Control Register (PMT_CTRL)
must be cleared since a set bit will cause the immediate assertion of wake event when WOL_EN
is set. The WUPS[1] bit will not clear if the internal MAC wakeup event is asserted.
4. Set the
Wake-On-Lan Wakeup Enable (WOL_EN)
Power Management Control Register
5. Set the
bit in the
PCI Power Management Control and Status Register
. Note that PME_EN must be set before entering the D3 state. If this bit is not set,
the internal PHY will be reset and placed in the General Power-Down state and the device will not
be able to detect wakeup frames.
6. To place the device in the D3 state, set the
Power Management State (PM_STATE)
field of the
Power Management Control and Status Register (PCI_PMCSR)
to 11b (‘D3’ state). The device will
enter D3
HOT
. Device behavior in this state is described in
Section 3.7.4.4, "The D3HOT State," on
On detection of an enabled wakeup frame, the device will assert the nPME signal. The nPME signal
will remain asserted until the
and/or the
bits are
cleared by the Host.
Note:
If waking from a reduced-power state causes the assertion of a device reset, bit 4 of the
Management Control Register (PMT_CTRL)
register (WUPS[1]) will be cleared.
3.7.7
Enabling Link Status Change (Energy Detect) Wake Events
The Host system must perform the following steps to enable LAN9420/LAN9420i to assert a PCI wake
event (nPME) on detection of an Ethernet link status change.
1. All transmit and receive operations must be halted:
a. All pending Ethernet TX and RX operations must be completed, and then the DMA controller and
MAC must be halted.
