SMSC LAN9420 Datasheet Download Page 19

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Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface

Datasheet

SMSC LAN9420/LAN9420i

Revision 1.22 (09-25-08)

DATASHEET

Table 2.5 PLL and Ethernet PHY Pins

NUM
PINS

NAME

SYMBOL

BUFFER

TYPE

DESCRIPTION

Crystal Input

ICLK

Crystal Input:

External 25MHz crystal input. This pin

can also be driven by a single-ended clock oscillator.
When this method is used, XO should be left
unconnected.

Crystal

Output

OCLK

Crystal Output:

External 25MHz crystal output.

Ethernet TX

Data Out

Negative

TPO-

AIO

Ethernet Transmit Data Out Negative:

The transmit

data outputs may be swapped internally with receive
data inputs when Auto-MDIX is enabled.

Ethernet TX

Data Out

Positive

TPO+

AIO

Ethernet Transmit Data Out Positive:

The transmit

data outputs may be swapped internally with receive
data inputs when Auto-MDIX is enabled.

Ethernet RX

Data In

Negative

TPI-

AIO

Ethernet Receive Data In Negative:

The receive data

inputs may be swapped internally with transmit data
outputs when Auto-MDIX is enabled.

Ethernet RX

Data In

Positive

TPI+

AIO

Ethernet Receive Data In Positive:

The receive data

inputs may be swapped internally with transmit data
outputs when Auto-MDIX is enabled.

External

PHY Bias

Resistor

EXRES

External PHY Bias Resistor:

Used for the internal

PHY bias circuits. Connect to an external 12.4K 1.0%
resistor to ground.

Summary of Contents for LAN9420

Page 1: ...atic payload padding and pad removal Loop back modes Flexible address filtering modes One 48 bit perfect address 64 hash filtered multicast addresses Pass all multicast Promiscuous mode Inverse filter...

Page 2: ...he product may contain design defects or errors known as anomalies which may cause the product s functions to deviate from published specifications Anomaly sheets are available upon request SMSC produ...

Page 3: ...Environments 25 3 2 3 PCI Master Interface 25 3 2 3 1 PCI Master Transaction Errors 25 3 2 4 PCI Target Interface 26 3 2 4 1 PCI Configuration Space Registers 26 3 2 4 2 Control and Status Registers...

Page 4: ...5 3 3 Hash Perfect Filtering 56 3 5 3 4 Inverse Filtering 56 3 5 4 Wakeup Frame Detection 57 3 5 4 1 Magic Packet Detection 59 3 5 5 Receive Checksum Offload Engine RXCOE 60 3 5 5 1 RX Checksum Calcul...

Page 5: ...iting the D0A State 77 3 7 4 4 The D3HOT State 77 3 7 4 4 1 Power Management Events in D3HOT 77 3 7 4 4 2 Exiting the D3HOT State 77 3 7 4 5 The D3COLD State 78 3 7 4 5 1 Power Management Events in D3...

Page 6: ...Tag Register VLAN1 130 4 4 10 VLAN2 Tag Register VLAN2 131 4 4 11 Wakeup Frame Filter WUFF 132 4 4 12 Wakeup Control and Status Register WUCSR 133 4 4 13 Checksum Offload Engine Control Register COE_...

Page 7: ...X Support and PCI Interface Datasheet SMSC LAN9420 LAN9420i 7 Revision 1 22 09 25 08 DATASHEET 5 7 PCI I O Timing 163 5 8 EEPROM Timing 165 5 9 Clock Circuit 166 Chapter 6 Package Outline 167 6 1 128...

Page 8: ...or Structures 40 Figure 3 16 Receive Descriptor 41 Figure 3 17 Transmit Descriptor 45 Figure 3 18 VLAN Frame 55 Figure 3 19 RXCOE Checksum Calculation 60 Figure 3 20 Type II Ethernet Frame 61 Figure 3...

Page 9: ...eup Generation Cases 59 Table 3 20 TX Checksum Preamble 63 Table 3 21 4B 5B Code Table 65 Table 3 22 Reset Map 79 Table 3 23 PHY Resets 80 Table 4 1 Register Bit Types 85 Table 4 2 System Control and...

Page 10: ...MDIX Support and PCI Interface Datasheet Revision 1 22 09 25 08 10 SMSC LAN9420 LAN9420i DATASHEET Table 5 13 LAN9420 LAN9420i Crystal Specifications 166 Table 6 1 LAN9420 LAN9420i 128 VTQFP Dimension...

Page 11: ...evice Magnetics To Ethernet PCI Bus LAN9420 LAN9420i 10 100 Ethernet PHY Ethernet PLL EEPROM optional GPIOs LEDs optional 25MHz 3 3V to 1 8V Regulator MAC Interface Layer MIL MAC Ethernet MAC PCI PCI...

Page 12: ...This feature enables easy integration into various ARM MIPS PowerPC designs LAN9420 LAN9420i supports the PCI Bus Power Management Interface Specification Revision 1 1 and provides the optional abili...

Page 13: ...transmit or receive transfer completed and other normal as well as error conditions Please refer to Section 3 4 DMA Controller DMAC on page 38 for more information 1 5 Ethernet MAC The transmit and re...

Page 14: ...ed to trigger interrupts with programmable polarity The GPOs are outputs only and have no means of generating interrupts Please refer to Section 4 2 5 General Purpose Input Output Configuration Regist...

Page 15: ...2 VDD33IO GPIO2 nLED3 VDD33IO VSS VDD33IO VDD33IO VDD18CORE VDD18CORE VSS VSS VDD33IO VSS PCInRST nINT nGNT PCICLK nPME nREQ VDD33IO VSS AD30 AD31 AD28 AD29 VSS AD27 AD26 VDD33IO AD24 AD25 NC 98 99 10...

Page 16: ...CI Device Select 1 PCI Parity PAR IPCI OPCI PCI Parity 1 PCI Parity Error nPERR IPCI OPCI PCI Parity Error 1 PCI System Error nSERR IPCI OPCI PCI System Error 1 PCI Interrupt nINT OPCI PCI Interrupt N...

Page 17: ...ess the serial EEPROM TX_EN TX_EN O8 TX_EN Signal Monitor This pin can also be configured to monitor the TX_EN signal on the internal MII port The EECS pin is deasserted so as to never unintentionally...

Page 18: ...ctivity Indicator nLED2 OD12 nLED2 Link Activity Indicator This pin can also function as the Ethernet Link and Activity Indicator LED and is driven low LED on when LAN9420 LAN9420i detects a valid lin...

Page 19: ...outputs may be swapped internally with receive data inputs when Auto MDIX is enabled 1 Ethernet TX Data Out Positive TPO AIO Ethernet Transmit Data Out Positive The transmit data outputs may be swapp...

Page 20: ...o VDD18CORE for proper operation Refer to the LAN9420 LAN9420i application note for additional connection information 1 3 3V Master Bias Power Supply VDD33BIAS P 3 3V Master Bias Power Supply Refer to...

Page 21: ...74 VDD33IO 106 TPI 11 VSS 43 VDD33IO 75 AD8 107 VDD33A 12 VSS 44 AD18 76 nCBE0 108 VSS 13 VDD33IO 45 AD17 77 AD7 109 EXRES 14 nINT 46 AD16 78 AD6 110 VSS 15 PCInRST 47 nCBE2 79 AD5 111 VDD33BIAS 16 P...

Page 22: ...Note Internal pull up resistors prevent unconnected inputs from floating Do not rely on internal resistors to drive signals external to LAN9420 LAN9420i When connected to a load that must be pulled hi...

Page 23: ...s LAN9420 LAN9420i to the PCI bus when it is functioning as a PCI Master It is used by the DMA engines to directly access the PCI Host s memory PCI Target Interface This interface connects LAN9420 LAN...

Page 24: ...SMSC LAN9420 LAN9420i DATASHEET 3 2 1 PCI Bridge PCIB Block Diagram Figure 3 1 PCI Bridge Block Diagram PCI PCI Bridge PCIB PCI Configuration Space CSR PCI Target PME Gating Interrupt Gating PM Signal...

Page 25: ...cates them within the flat PCI address space 3 2 3 1 PCI Master Transaction Errors In the event of an error during a descriptor read or during a transmit data read the DMA controller will generate a M...

Page 26: ...n page 149 for further details These registers exist in the configuration space 3 2 4 2 Control and Status Registers CSR The PCI Target Interface allows PCI bus masters to directly access the LAN9420...

Page 27: ...erformed A software reset is accomplished by setting the SRST bit of the BUS_MODE register 3 2 4 4 PCI Discard Timer When the PCI master performs a read of LAN9420 LAN9420i the PCI Bridge will fetch t...

Page 28: ...enerate a system interrupt upon timeout Free Run Counter FRC A 32 bit free running counter with a 160 ns resolution EEPROM Controller EPC An optional external Serial EEPROM may be used to store the de...

Page 29: ...k upon a Figure 3 6 Interrupt Controller Block Diagram PHY Interrupt GPIO0 Interrupt GPIO0_INT_EN INT_CTL Register RW GPIO0_INT INT_STS Register 0 to 1 DETECT SW_INT_EN INT_CTL Register RW SW_INT INT_...

Page 30: ...rtion timer does not affect WAKE_INT This interrupt event is able to assert IRQ regardless of the state of the de assertion timer The IRQ_INT status bit in the INT_CFG register reflects the aggregate...

Page 31: ...on this register 3 3 5 EEPROM Controller EPC LAN9420 LAN9420i may use an optional external EEPROM to store the default values for the MAC address PCI Subsystem ID and PCI Subsystem Vendor ID The PCI S...

Page 32: ...responsibility of the Host LAN driver software to set the IEEE address by writing to the MAC s ADDRH and ADDRL registers 3 3 5 3 EEPROM Host Operations After the EEPROM controller has finished reading...

Page 33: ...they may be used to monitor internal MII signals 3 3 5 3 1 SUPPORTED EEPROM OPERATIONS The EEPROM controller supports the following EEPROM operations under Host control via the E2P_CMD register The o...

Page 34: ...rase All If erase write operations are enabled in the EEPROM this command will initiate a bulk erase of the entire EEPROM The EPC_TO bit is set if the EEPROM does not respond within 30ms Figure 3 8 EE...

Page 35: ...rite Enable Enables the EEPROM for erase and write operations The EEPROM will allow erase and write operations until the Erase Write Disable command is sent or until power is cycled Note The EEPROM de...

Page 36: ...e in the E2P_DATA register WRITE Write Location If erase write operations are enabled in the EEPROM this command will cause the contents of the E2P_DATA register to be written to the EEPROM location s...

Page 37: ...the E2P command E2P_CMD register If the first byte read from the EEPROM is not A5h it is assumed that the EEPROM is not present or not programmed and the RELOAD operation will fail The EEPROM Loaded b...

Page 38: ...tilizes descriptors to efficiently move data from source to destination with minimal Host intervention Descriptors are 4 DWORD 16 byte aligned data structures in Host memory that inform the DMAC of th...

Page 39: ...eceive and transmit descriptors RCH RDES1 24 and TCH TDES1 24 Each descriptor s list resides in Host memory Each descriptor can point to a maximum of two buffers This enables the use of two physically...

Page 40: ...vision 1 22 09 25 08 40 SMSC LAN9420 LAN9420i DATASHEET Figure 3 15 Ring and Chain Descriptor Structures DESCRIPTOR 0 BUFFER 1 BUFFER 2 DESCRIPTOR 1 BUFFER 1 BUFFER 2 DESCRIPTOR n BUFFER 1 BUFFER 2 Ri...

Page 41: ...s cleared by DMAC or until the DMAC is in STOPPED state whichever comes first DMAC Actions Reads this bit to determine ownership of the descriptor block and its associated buffer s The DMAC clears thi...

Page 42: ...on writes 12 LE Length Error When set this bit indicates that the actual length does not match with the Length Type field of the incoming frame Host Actions Checks this bit to determine status DMAC A...

Page 43: ...ctions Checks this bit to determine status DMAC Actions Sets clears this bit to define status 3 ME MII Error When set this bit indicates that a receive error was detected during frame reception RX_ER...

Page 44: ...is next descriptor address 23 22 RESERVED Host Actions Cleared on writes and ignored on reads DMAC Actions Ignored on reads DMAC does not write to RDES1 21 11 RBS2 Receive Buffer 2 Size Indicates the...

Page 45: ...aligned the resulting behavior is undefined RCH is one Descriptor chaining is in use and this field contains the pointer to the next descriptor in Host memory The descriptor must be 4 DWORD 16 byte a...

Page 46: ...he frame transmission or when the buffers that are associated with this descriptor are empty By clearing this bit the DMAC closes the descriptor block and passes ownership to the Host If the DMAC fetc...

Page 47: ...24 288 bit times during transmission Host Actions Checks this bit to determine status DMAC Actions Sets clears this bit to define status 1 Reserved 0 DE Deferred When set indicates that the DMA Contr...

Page 48: ...etermine if this is the final descriptor in the ring 24 TCH Second Address Chained When set indicates that the second address in the descriptor is the next descriptor address rather than the second bu...

Page 49: ...nsmitter on Table 3 11 TDES2 Bit Fields BITS DESCRIPTION 31 0 Buffer 1 Address Pointer This is the physical address of buffer 1 There are no limitations on the buffer address alignment Host Actions In...

Page 50: ...izes a descriptor for itself it can begin working on the descriptor 2 Once set to the running state the DMA controller reads the Host memory buffer to collect the first descriptor The starting address...

Page 51: ...the suspended state when a receive buffer is unavailable If a frame arrives when the receiver is in the suspended state the receive engine re fetches the descriptor and if now owned by the DMA control...

Page 52: ...ce consumption of 2 032 bytes leaving 4 bytes to spare this is the basis for the 86 fragment rule mentioned above 3 4 10 DMAC Interrupts As described in earlier sections there are numerous events that...

Page 53: ...Receive packets Checksum offload engine for calculation of layer 3 transmit and receive checksum The MAC block includes a MAC Interface Layer MIL The MIL provides a FIFO interface between the DMAC an...

Page 54: ...and processed by the MAC and are passed on The MAC also transmits control frames pause command under software control The software driver requests the MAC to transmit a control frame and gives the val...

Page 55: ...filter the MAC does not receive the packet The Host has the option of accepting or ignoring the packet Figure 3 18 VLAN Frame Table 3 13 Address Filtering Modes MCPAS PRMS INVFILT HFILT HPFILT DESCRIP...

Page 56: ...ster A value of 00000 selects Bit 0 of the multicast hash table low register and a value of 11111 selects Bit 31 of the multicast hash table high register 3 5 3 3 Hash Perfect Filtering In hash perfec...

Page 57: ...mode is enabled the remote wakeup function receives all frames addressed to the MAC It then checks each frame against the enabled filter and recognizes the frame as a remote wakeup frame if it passes...

Page 58: ...Bit Definitions FILTER i BYTE MASK DESCRIPTION BITS DESCRIPTION 31 RESERVED 30 0 Byte Mask If bit j of the byte mask is set the CRC machine processes byte pattern offset j of the incoming frame Otherw...

Page 59: ...n the Host clears the MPEN bit normal receive operation will resume Please refer to Section 4 4 12 Wakeup Control and Status Register WUCSR on page 133 for additional information on this register In M...

Page 60: ...55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 CRC It should be noted that Magic Packet detection can be performed when LAN9420 LAN9420i is in any power management state 3...

Page 61: ...Type II Ethernet Frame Figure 3 21 Ethernet Frame with VLAN Tag Figure 3 22 Ethernet Frame with Length Field and SNAP Header DST SRC p r o t 0 1 2 3 L3 Packet F C S Calculate Checksum DST SRC 8 1 0 0...

Page 62: ...mmodate the checksum Setting the RX_COE_EN bit in the Checksum Offload Engine Control Register COE_CR enables the RXCOE while the RX_COE_MODE bit selects the operating mode When the RXCOE is disabled...

Page 63: ...e the byte offset at which the data checksum calculation will begin The checksum calculation will begin at this offset and will continue until the end of the packet The data checksum calculation must...

Page 64: ...Mbps 10BASE T Ethernet operation The PHY block includes Support for auto negotiation Automatic polarity detection and correction HP Auto MDIX Energy detect Duplex link activity and speed indicator LE...

Page 65: ...o by the hexadecimal values of their corresponding data nibbles 0 through F The remaining code groups are given letter designations with slashes on either side For example an IDLE code group is I a tr...

Page 66: ...0 J First nibble of SSD translated to 0101 following IDLE else RX_ER Sent for rising TX_EN 10001 K Second nibble of SSD translated to 0101 following J else RX_ER Sent for rising TX_EN 01101 T First ni...

Page 67: ...ence clock and generates the 125MHz clock used to drive the 125 MHz logic and the 100BASE Tx Transmitter Figure 3 26 Receive Data Path 3 6 2 100BASE TX Receive The receive data path is shown in Figure...

Page 68: ...00 bytes 40us This window ensures that a maximum packet size of 1514 bytes allowed by the IEEE 802 3 standard can be received with no interference If no IDLE symbols are detected within this time peri...

Page 69: ...al Link Pulses NLPs to maintain communications with the remote link partner 3 6 3 3 10M Transmit Drivers The Manchester encoded data is sent to the analog transmitter where it is shaped and filtered b...

Page 70: ...on is fully defined in clause 28 of the IEEE 802 3 specification Once auto negotiation has completed information about the resolved link can be passed back to the controller via the internal Serial Ma...

Page 71: ...e speed of the link based on either 100M MLT 3 symbols or 10M Normal Link Pulses In this case the link is presumed to be half duplex per the IEEE standard This ability is known as Parallel Detection T...

Page 72: ...nd TX line pairs are interchangeable special PCB design considerations are needed to accommodate the symmetrical magnetics and termination of an Auto MDIX design The Auto MDIX function can be disabled...

Page 73: ...led 3 6 9 PHY Resets In addition to a chip level reset the PHY supports two software initiated resets These are discussed in the following sections 3 6 9 1 PHY Soft Reset via PMT_CTRL bit 10 PHY_RST T...

Page 74: ...ated External Signals and Power Supplies The following external signals are provided in support of PCI power management nPME LAN9420 LAN9420i can assert this signal upon detection of an enabled power...

Page 75: ...states as well as the events required to cause state transitions LAN9420 LAN9420i s behavior is dependant on the device s VAUXDET pin the device s ability to detect wake events in D3COLD Specific beha...

Page 76: ...he following conditions State transitions are illustrated in Figure 3 28 on page 75 D0U to D3HOT T1 This transition occurs when the Host system selects the D3 state in the Power Management State PM_ST...

Page 77: ...hen all power supplies are turned off PCInRST X PM_STATE XXb VAUXDET 1 to 0 PWRGOOD 1 to 0 For example total power failure 3 7 4 4 The D3HOT State In this state the PCI power is on but normal Ethernet...

Page 78: ...n this state the PCI 3 3Vaux power is on but normal Ethernet receive and transmit operation is disabled In D3COLD power is reduced by disabling the internal PLL and derivative clocks 3 7 4 5 1 POWER M...

Page 79: ...the PHY Reset PHY_RST in the Power Management Control Register PMT_CTRL Refer to section Section 3 6 9 1 PHY Soft Reset via PMT_CTRL bit 10 PHY_RST on page 73 for more information PHY Soft Reset PHY_...

Page 80: ...al Power Down mode Specific PHY reset conditions and the state of the PHY following reset are detailed in Table 3 23 below The state transitions noted in this table refer to those specified in Section...

Page 81: ...pending DMA transactions to complete Upon completion no further transactions are permitted 2 The MAC must be configured to detect the desired wake event This process is explained in Section 3 5 4 Wake...

Page 82: ...PS 0 in the Power Management Control Register PMT_CTRL must be cleared since a set bit will cause the immediate assertion of wake event when ED_EN is set The WUPS 0 bit will not clear if the internal...

Page 83: ...d within the MAC The fourth group are the PHY control registers These registers reside within the PHY and are accessed indirectly through MCSR within the MAC The fifth set of registers is the PCI Conf...

Page 84: ...SR Memory Map M A C C ontrol and Status R egisters M C SR s BA 7Ch BA 80h R ESER VED D O N O T U SE BA 54h BA B0h BA R ESER VED D O N O T U SE BA 1FCh BA 58h D M A C C ontrol and Status R egisters D C...

Page 85: ...ll stay low until the bit is read After a read the bit will remain low but will change to high if the condition that caused the bit to go low is removed If the bit has not been read the bit will remai...

Page 86: ...tus Register 00CCh INT_CFG Interrupt Configuration Register 00D0h GPIO_CFG General Purpose IO Configuration 00D4h GPT_CFG General Purpose Timer Configuration 00D8h GPT_CNT General Purpose Timer Curren...

Page 87: ...on ID_REV This register contains the device ID and block revision Note 4 1 Default value is dependent on device revision Offset 00C0h Size 32 bits BITS DESCRIPTION TYPE DEFAULT 31 16 Chip ID This 16 b...

Page 88: ...gers the software interrupt R W 0b 14 RESERVED RO 13 Master Bus Error Interrupt Enable MBERR_INT_EN When set high the Master Bus Error is enabled to generate an interrupt R W 0b 12 Slave Bus Error Int...

Page 89: ...en set indicates that the PCI Target Interface has detected an error when the Host attempted to access the LAN9420 LAN9420i CSR The interrupt is cleared by writing a 1 to this bit Writing a 0 has no e...

Page 90: ...d The particular source of the interrupt can be determined by the WUPS field of the Power Management Control Register PMT_CTRL Both WUPS bits must be cleared in order to clear WAKE_INT Writing to the...

Page 91: ...nable IRQ_EN When cleared the IRQ output to the PCIB is disabled and will be permanently de asserted When set the IRQ output functions normally R W 0b 17 10 RESERVED RO 9 Interrupt De assertion Interv...

Page 92: ...t the corresponding INT_STS register bit GPIO interrupts must also be enabled in GPIOx_INT_EN in the INT_EN register Bits are assigned as follows GPIO0 bit 24 GPIO1 bit 25 GPIO2 bit 26 Note GPIO input...

Page 93: ...ESERVED RO 4 3 GPO Data 3 4 GPODn The value written is reflected on GPOn Bits are assigned as follows GPO3 bit 3 GPO4 bit 4 R W 00b 2 0 GPIO Data 0 2 GPIODn When enabled as an output the value written...

Page 94: ...eneral Purpose Timer GPT on page 30 for more information on the General Purpose Timer Offset 00D4h Size 32 bits BITS DESCRIPTION TYPE DEFAULT 31 30 RESERVED RO 29 General Purpose Timer Enable TIMER_EN...

Page 95: ...08 DATASHEET 4 2 7 General Purpose Timer Current Count Register GPT_CNT This register reflects the current value of the general purpose timer Offset 00D8h Size 32 bits BITS DESCRIPTION TYPE DEFAULT 3...

Page 96: ...haracteristics for the RX and TX DMA engines Offset 00DCh Size 32 bits BITS DESCRIPTION TYPE DEFAULT 31 28 RESERVED RO 27 RESERVED R W 0b 26 25 RX TX Arbitration Priority Select CSR_RXTXWEIGHT This fi...

Page 97: ...9 Wake On Lan Wakeup Enable WOL_EN When set the MAC Wake Detect signal is enabled as a wake event and will set the PME_STATUS in the PCI_PMCSR The MAC Wake Detect signal can be programmed for asserti...

Page 98: ...free running 6 25Mhz counter FRC Offset 00F4h Size 32 bits BITS DESCRIPTION TYPE DEFAULT 31 0 Free Running Counter FR_CNT This field reflects the value of a free running 32 bit counter At reset the co...

Page 99: ...the specified EEPROM address This bit will remain set until the operation is complete In the case of a read this means that the Host can read valid data from the E2P data register The E2P_CMD and E2P_...

Page 100: ...f erase write operations are enabled in the EEPROM this command will cause the contents of the E2P_DATA register to be written to every EEPROM memory location 30 28 101 ERASE Erase Location If erase w...

Page 101: ...at the MAC address and SSVID SSID programming have completed normally This bit is set after a successful load of the MAC address and SSVID SSID after power up or after a RELOAD command has completed R...

Page 102: ...2P_CMD register to perform read and write operations with the serial EEPROM Note 4 3 Following reset the default value of the EEPROM Data reflects the last value read by the EEPROM controller during a...

Page 103: ...ister 0008h RX_POLL_DEMAND Receive Poll Demand Register 000Ch RX_ BASE_ADDR Receive List Base Address Register 0010h TX_BASE_ADDR Transmit List Base Address Register 0014h DMAC_STATUS DMA Controller S...

Page 104: ...t transfer the length specified in the PBL each time it starts a burst transfer PBL can be programmed with permissible values of 1 2 4 8 16 and 32 Any other value will result in undefined behavior R W...

Page 105: ...e 32 bits BITS DESCRIPTION TYPE DEFAULT 31 0 Transmit Poll Demand TPD When written with any value the DMAC will check for frames to be transmitted If no descriptor is available the transmit process re...

Page 106: ...Size 32 bits BITS DESCRIPTION TYPE DEFAULT 31 0 Receive Poll Demand RPD When written with any value the DMAC will check for receive descriptors If no descriptors are available the receive process retu...

Page 107: ...BASE_ADDR must be 4 DWORD 16 byte aligned e g Reserved address bits 3 0 must be 0 Offset 000Ch Size 32 bits BITS DESCRIPTION TYPE DEFAULT 31 4 Start of Receive List SRL This field points to the start...

Page 108: ...BASE_ADDR must be 4 DWORD 16 byte aligned e g Reserved address bits 3 0 must be 0 Offset 0010h Size 32 bits BITS DESCRIPTION TYPE DEFAULT 31 4 Start of Transmit List STL This field points to the start...

Page 109: ...ist of bits DMAC_STATUS 0 Transmit interrupt TI DMAC_STATUS 2 Transmit buffer unavailable TU DMAC_STATUS 6 Receive interrupt RI R WC 0b 15 Abnormal Interrupt Summary AIS This bit is the logical OR of...

Page 110: ...nt not owned receive descriptor fetches RU is set only when the previous receive descriptor was owned by the DMA controller RU remains asserted until it is cleared by software R WC 0b 6 Receive Interr...

Page 111: ...when the transmit process was previously stopped If no descriptor can be acquired the transmit process enters the Suspended state If the current descriptor is not owned by the DMA Controller the tran...

Page 112: ...etting the RX_BASE_ADDR the DMA Controller s behavior will be undefined When cleared the Receive process enters the Stopped state after completing the reception of the current frame The next descripto...

Page 113: ...bles the following bits DMAC_STATUS 1 Transmit process stopped TPS DMAC_STATUS 5 RESERVED DMAC_STATUS 7 Receive buffer unavailable RU DMAC_STATUS 8 Receive process stopped RPS R W 0b 14 RESERVED R W 0...

Page 114: ...Transmit Process Stopped TPS_EN The Transmit Process Stopped Interrupt is enabled only when this bit and the Abnormal Interrupt Summary Enable bit bit 15 are set R W 0b 0 Transmit Interrupt TI_EN The...

Page 115: ...Overflow MIL_OVER Overflow bit for the MIL_FIFO_FULL counter This bit is automatically cleared on a read RC 0b 27 17 MIL RX FIFO Full Counter MIL_FIFO_FULL This field indicates the number of frames mi...

Page 116: ...SHEET 4 3 10 Current Transmit Buffer Address Register TX_BUFF_ADDR This register points to the current transmit buffer address being read by the DMAC Offset 0050h Size 32 bits BITS DESCRIPTION TYPE DE...

Page 117: ...ASHEET 4 3 11 Current Receive Buffer Address Register RX_BUFF_ADDR This register points to the current receive buffer address being read by the DMAC Offset 0054h Size 32 bits BITS DESCRIPTION TYPE DEF...

Page 118: ...egister MCSR Map OFFSET SYMBOL REGISTER NAME 0080h MAC_CR MAC Control 0084h ADDRH MAC Address High 0088h ADDRL MAC Address Low 008Ch HASHH Multicast Hash Table High 0090h HASHL Multicast Hash Table Lo...

Page 119: ...full duplex mode 0 Normal No feedback 1 Internal through MII In internal loopback mode the TX frame is received by the Internal MII interface and sent back to the MAC without being sent to the PHY Not...

Page 120: ...1 Disable Broadcast Frames BCAST When set disables the reception of broadcast frames When reset forwards all broadcast frames to the application Note When wake up frame detection is enabled via the WU...

Page 121: ...slot times To give the user more flexibility the BOLMT value forces the number of bits to be used from the LFSR counter to a predetermined value as in the table below Thus if the value of K 10 the MAC...

Page 122: ...be enabled by setting the Start Stop Receive bit SR bit of the DMA Controller Control Operation Mode Register DMAC_CONTROL prior to enabling the receiver by setting RXEN Note In order to successfully...

Page 123: ...ss High Register ADDRH This register contains the upper 16 bits of the physical address of the MAC where ADDRH 15 8 is the 6th octet of the RX frame Offset 0084h Size 32 bits BITS DESCRIPTION TYPE DEF...

Page 124: ...is 12 34 56 78 9A BC the ADDRL and ADDRH registers would be programmed as shown in Figure 4 2 The values required to automatically load this configuration from the EEPROM are shown in Section 3 3 5 1...

Page 125: ...rmine the bit within the register A value of 00000 selects Bit 0 of the Multicast Hash Table Lo register and a value of 11111 selects the Bit 31 of the Multicast Hash Table Hi register If the correspo...

Page 126: ...ATASHEET 4 4 5 Multicast Hash Table Low Register HASHL This register defines the lower 32 bits of the Multicast Hash Table Please refer to Section 4 4 4 Multicast Hash Table High Register HASHH on pag...

Page 127: ...he PHY that this will be a write operation using the MII data register If this bit is not set this will be a read operation packing the data in the MII data register R W 0b 0 MII Busy MIIBZY This bit...

Page 128: ...data from the PHY register whose index is specified in the MII Access Register Refer toSection 4 4 6 MII Access Register MII_ACCESS on page 127 for further details Note The MIIBZY bit in the MII_ACCE...

Page 129: ...et When reset the MAC resets the packet filter bit in the receive packet status The MAC always passes the data of all frames it receives including flow control frames to the application Frames that do...

Page 130: ...o determine the protocol value to use to indicate the existence of a VLAN tag When using the RXCOE this value may only be changed if the RX path is disabled If it is desired to change this value durin...

Page 131: ...e VLAN tag field to identify VLAN2 frames For VLAN frames the legal frame length is increased from 1518 bytes to 1522 bytes Offset 00A4h Size 32 bits BITS DESCRIPTION TYPE DEFAULT 31 16 RESERVED RO 15...

Page 132: ...DWORD in the Wakeup Frame Filter filter 0 byte mask The second value written to this location is loaded to the second DWORD in the wakeup Frame Filter filter 1 byte mask and so on Once all eight DWORD...

Page 133: ...om power saving mode on receipt of a global unicast frame A global unicast frame has the MAC Address 0 bit set to 0 0b 8 7 RESERVED RO 6 Remote Wakeup Frame Received WUFR The MAC sets this bit upon re...

Page 134: ...NAP header prior to beginning its checksum calculation In its default mode the calculation will always begin 14 bytes into the frame The COE_MODE may only be changed if the RX path is disabled If it i...

Page 135: ...egisters below Note The NASR Not Affected by Software Reset designation is only applicable when bit 15 of the PHY Basic Control Register Reset is set Table 4 7 PHY Control and Status Registers INDEX I...

Page 136: ...Mbps Ignored if Auto Negotiation is enabled 0 12 1 R W 1b 12 Auto Negotiation Enable 1 enable auto negotiate process overrides 0 13 and 0 8 0 disable auto negotiate process R W 1b 11 Power Down 1 Gene...

Page 137: ...s with full duplex ability RO 1b 11 10BASE T Half Duplex 1 10Mbps with half duplex 0 no 10Mbps with half duplex ability RO 1b 10 6 RESERVED RO 5 Auto Negotiate Complete 1 auto negotiate process comple...

Page 138: ...tasheet Revision 1 22 09 25 08 138 SMSC LAN9420 LAN9420i DATASHEET 4 5 3 PHY Identifier 1 Index In Decimal 2 Size 16 bits BITS DESCRIPTION TYPE DEFAULT 15 0 PHY ID Number Assigned to the 3rd through 1...

Page 139: ...sion 1 22 09 25 08 DATASHEET 4 5 4 PHY Identifier 2 Index In Decimal 3 Size 16 bits BITS DESCRIPTION TYPE DEFAULT 15 10 PHY ID Number b Assigned to the 19th through 24th bits of the OUI R W C0C3h 9 4...

Page 140: ...YPE DEFAULT 15 RESERVED R W 0b 14 RESERVED RO 13 Remote Fault 1 remote fault detected 0 no remote fault R W 0b 12 RESERVED R W 11 10 Pause Operation See Note 4 5 00 No PAUSE 01 Symmetric PAUSE 10 Asym...

Page 141: ...lt 1 remote fault detected 0 no remote fault RO 0b 12 RESERVED RO 11 10 Pause Operation 00 No PAUSE supported by partner station 01 Symmetric PAUSE supported by partner station 10 Asymmetric PAUSE sup...

Page 142: ...detection logic 0 no fault detected by parallel detection logic RO LH 0b 3 Link Partner Next Page Able 1 link partner has next page ability 0 link partner does not have next page ability RO 0b 2 Next...

Page 143: ...bits BITS DESCRIPTION TYPE DEFAULT 15 14 RESERVED RO 13 EDPWRDOWN Enable the Energy Detect Power Down mode 0 Energy Detect Power Down is disabled 1 Energy Detect Power Down is enabled R W 0b 12 2 RES...

Page 144: ...ER 0 REGISTER 4 13 12 8 8 7 6 5 000b 10BASE T Half Duplex Auto negotiation disabled 000 N A 001b 10BASE T Full Duplex Auto negotiation disabled 001 N A 010b 100BASE TX Half Duplex Auto negotiation dis...

Page 145: ...or reversed connection 1 Enable Auto MDIX 27 13 must be set to 0 R W 0b 13 Auto MDIX State Only effective when 27 15 1 otherwise ignored When 27 14 0 manually set MDIX state 0 no crossover TPO output...

Page 146: ...0 not source of interrupt RO LH 0b 6 INT6 1 Auto Negotiation complete 0 not source of interrupt RO LH 0b 5 INT5 1 Remote Fault Detected 0 not source of interrupt RO LH 0b 4 INT4 1 Link Down link statu...

Page 147: ...I Interface Datasheet SMSC LAN9420 LAN9420i 147 Revision 1 22 09 25 08 DATASHEET 4 5 12 Interrupt Mask Index In Decimal 30 Size 16 bits BITS DESCRIPTION TYPE DEFAULT 15 8 RESERVED RO 7 0 Mask Bits 1 i...

Page 148: ...ations Index In Decimal 31 Size 16 bits BITS DESCRIPTION TYPE DEFAULT 15 13 RESERVED RO 12 Autodone Auto negotiation done indication 0 Auto negotiation is not done or disabled or not active 1 Auto neg...

Page 149: ...ls Registers in offsets 00h 03Fh are standard PCI header registers as described in the PCI Local Bus Specification Revision 3 0 Please refer to the specification for further details Register 78h is a...

Page 150: ...LAN9420 LAN9420i then the default values in the table are used Table 4 10 Standard PCI Header Registers Supported CONFIGURATION SPACE OFFSET REGISTER NAME READ WRITE DEFAULT EEPROM CONFIGURABLE 00h 01...

Page 151: ...N_D2 This bit is cleared since LAN9420 LAN9420i does not support the D2 power management state RO 0b 28 PME Support from D1 PME_IN_D1 This bit is cleared since LAN9420 LAN9420i does not support the D1...

Page 152: ...ation Version VERSION 2 0 This device complies with Revision 1 1 of the PCI Bus Power Management Interface Specification RO 010b 15 8 Next Item Offset NEXT_OFFSET 7 0 There is only a single item in th...

Page 153: ...eset on assertion of a power on reset or PCI reset PCInRST When the VAUXDET input pin is high this bit is unaffected by assertion of PCI reset PCInRST In this case the bit will maintain its setting un...

Page 154: ...is dependant on the setting of the VAUXDET signal as noted in the description 1 0 Power Management State PM_STATE This field sets the current PM state 00b D0 01b RESERVED 10b RESERVED 11b D3 Operatio...

Page 155: ...hen AC power is switched on or off In addition voltage transients on the AC power line may appear on the DC output If this possibility exists it is suggested that a clamp circuit be used Note 5 2 This...

Page 156: ...cy temperature and supply voltage as well as external source sink requirements 5 3 1 D0 Normal Operation with Ethernet Traffic Table 5 1 D0 Normal Operation Supply and Current Typical PARAMETER TYPICA...

Page 157: ...Air TA 25 o C 10BASE T Full Duplex Supply current VDD33IO VDD33BIAS VDD33A 40 mA Power Dissipation Device Only 131 mW Power Dissipation Device and Ethernet components 502 mW Ambient Operating Tempera...

Page 158: ...n Device and Ethernet components 19 mW Ambient Operating Temperature in Still Air TA 25 o C 10BASE T Full Duplex Supply current VDD33IO VDD33BIAS VDD33A 6 mA Power Dissipation Device Only 19 mW Power...

Page 159: ...5 6 I O Buffer Characteristics PARAMETER SYMBOL MIN TYP MAX UNITS NOTES IS Type Input Buffer Low Input Level High Input Level Negative Going Threshold Positive Going Threshold SchmittTrigger Hysteres...

Page 160: ...PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Peak Differential Output Voltage High VPPH 950 1050 mVpk Note 5 10 Peak Differential Output Voltage Low VPPL 950 1050 mVpk Note 5 10 Signal Amplitude Symmetry...

Page 161: ...n revision 3 0 Refer to the Conventional PCI 3 0 Specification for PCI timing details and parameters 5 5 1 Equivalent Test Load Non PCI Signals Output timing specifications assume the 25pF equivalent...

Page 162: ...14 This slew rate must be met across the minimum peak to peak portion of the clock waveform as shown in Figure 5 2 Figure 5 2 PCI Clock Timing Table 5 9 PCI Clock Timing Values SYMBOL DESCRIPTION MIN...

Page 163: ...VDD33IO overdrive Vmax specifies the maximum peak to peak waveform allowed for testing input timing Figure 5 3 PCI I O Timing Table 5 10 PCI I O Timing Measurement Conditions SYMBOL VALUE UNITS Vth 0...

Page 164: ...easserted asynchronously with respect to the PCICLK signal Table 5 11 PCI I O Timing Values SYMBOL DESCRIPTION MIN TYP MAX UNITS tval PCICLK to signal valid delay bussed signals 2 11 ns tval nREQ PCIC...

Page 165: ...570 ns tcshckh EECS high before rising edge of EECLK 1070 ns tcklcsl EECLK falling edge to EECS low 30 ns tdvckh EEDIO valid before rising edge of EECLK OUTPUT 550 ns tckhdis EEDIO disable after risi...

Page 166: ...for the Transmitter Clock Frequency is specified by IEEE 802 3u as 50 PPM Note 5 20 0o C for commercial version 40o C for industrial version Note 5 21 70o C for commercial version 85o C for industria...

Page 167: ...roller with HP Auto MDIX Support and PCI Interface Datasheet SMSC LAN9420 LAN9420i 167 Revision 1 22 09 25 08 DATASHEET Chapter 6 Package Outline 6 1 128 VTQFP Package Figure 6 1 LAN9420 LAN9420i 128...

Page 168: ...25mm per side D1 and E1 are maximum plastic body size dimensions including mold mismatch 4 The pin 1 identifier may vary but is always located within the zone indicated Table 6 1 LAN9420 LAN9420i 128...

Page 169: ...Supported on page 150 Changed default values of Min_Gnt and Max_Lat to 02h and 04h respectively Section 3 5 5 1 RX Checksum Calculation on page 63 Changed last line of RX checksum calculation to check...

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SMSC LAN9420, Datasheet

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