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Si53119-EVB

Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [email protected] • www.skyworksinc.com

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Rev. 0.1 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • October 17, 2021

2.  Jumpers

Jumpers can be set per the diagram above. Please refer to the Si53119-A01AGM data sheet for a description on
how the pin states affect the device. (M--Insert link here to data sheet when it’s released.)

1.  P15 and P17 disable I2C control when shorted.
2.  P14 can be used to set PWRGD# (VDD or Ground).
3.  P16 can be used to set outputs clocks to either 100MHz or 133MHz (controls the 100_133@# pin).
4.  Jumpers J11, J14, and J19 are tri-level jumpers that control BYPASS/BWSEL, SA_0, and SA_1 

respectively.

5.  P1 needs to be shorted to enable generation of VDD/2.

Default jumper setting on the EVB:

1.  P15, P17 are shorted, disabling I

2

C.

2.  P14 is shorted to VDD (PWRGD# = High).
3.  P16 is shorted to VDD (100_133# = High).
4.  BYPASS/BWSEL, SA_0, SA_1 are all pulled low (J11, J14, J19 pulled to ground).
5.  P1 is shorted to enable VDD/2 (needed for tristate input pin conditioning).

3.  Input and Power Supply Sequencing

The Si53119 should be powered up with supply at both the VDD and VDD_IO nodes (at the jumpers available on
the EVB). A 100 MHz or 133 MHz HCSL input clock should be applied to pins 8 and 9, and should comply with
HCSL formats. There is no internal or onboard resistive termination, therefore HCSL termination needs to be
provided at the input if needed by the driver. The input clock should be applied only after the supplies are stable.

4.  Quick Start Guide:

1.  Enable supply on the VDD pin.
2.  Enable supply on the VDDIO pin.
3.  Apply input clock on SMA connectors J26, J29 and measure the return path clock on J32, J33 (as shown 

below).

Figure 4. Clock Return Path

a. The input clock measured at J32, J33 needs a 50-ohm termination on the scope.
b. The attenuation will be 1:10 after the above termination. Appropriate scaling (10x) needs to be set at 

the scope to adjust for the scaling.

4.  The output clocks are now set up and can be measured on an oscilloscope or frequency domain 

measurement instrument.

 

Summary of Contents for Si53119

Page 1: ... to evaluate the Si53119 A01AGM 19 output PCIe buffer in zero delay and non zero delay modes Features 10 inch traces to evaluate signal integrity at the longest trace lengths The signal traces of the input and outputs have a single ended impedance of 50 and differential impedance of 100 The series resistance on the outputs are set to match to this impedance design DC pin controls per data sheet sp...

Page 2: ...14 DIFF_15 DIFF_15 DIFF_16 DIFF_16 DIFF_17 DIFF_17 DIFF_18 DIFF_18 Si53119 U1 100M_133M 3 HBW _BYPASS_LBW 4 PW RGD_PW RDN 5 CLK_IN 8 CLK_IN 9 SA_0 10 SDA 11 SCL 12 SA_1 13 FBOUT_NC 14 FBOUT_NC 15 DIF_10 47 DIF_10 48 DIF_11 49 DIF_11 50 DIF_12 53 DIF_12 54 DIF_13 55 DIF_13 56 DIF_14 59 DIF_14 60 DIF_15 61 DIF_15 62 DIF_16 65 DIF_16 66 DIF_17 67 DIF_17 68 DIF_18 71 DIF_18 72 VDDA 1 GNDA 2 GND 6 VDDR...

Page 3: ... Inc Phone 781 376 3000 Fax 781 376 3100 sales skyworksinc com www skyworksinc com 3 Rev 0 1 Skyworks Proprietary Information Products and Product Information are Subject to Change Without Notice October 17 2021 Figure 2 Schematic 2 ...

Page 4: ...ns Inc Phone 781 376 3000 Fax 781 376 3100 sales skyworksinc com www skyworksinc com Rev 0 1 Skyworks Proprietary Information Products and Product Information are Subject to Change Without Notice October 17 2021 Figure 3 Schematic 3 ...

Page 5: ...SA_0 SA_1 are all pulled low J11 J14 J19 pulled to ground 5 P1 is shorted to enable VDD 2 needed for tristate input pin conditioning 3 Input and Power Supply Sequencing The Si53119 should be powered up with supply at both the VDD and VDD_IO nodes at the jumpers available on the EVB A 100 MHz or 133 MHz HCSL input clock should be applied to pins 8 and 9 and should comply with HCSL formats There is ...

Page 6: ...he EVB Once the EVB has been set up the following can be evaluated 1 Signal integrity of the device when driving 10 inch 100 ohm differential traces 2 Effect of capacitance load on output signal integrity 3 Output to output skew over 10 inch traces 4 Input to output prorogation delay in BYPASS HBW and LBW modes using the input clock return path 5 Measuring the power consumption of the device 6 Mod...

Page 7: ...FB5 220Ohm L0402 BLM 15EG221SN1 M uRata 7 42 J55J56J47J48J49J50J67J68J59J60J61J62J34 J36J37J38J39J40J51J52J53J54J57J58J63J64 J65J66J69J70J71J72J41J42J43J44J46J45J26 J29J32J33 SM A CONN SM A ST 142 0701 201 JohnsonComponents 8 3 J11J14J19 HEADER2x3 CONN2X3_4PIN TSW 103 07 T D Samtec 9 2 J30J31 2x6 35m m CONN TB 1714955 1714955 PhoenixContact 10 3 P1P15P17 JUM PER CONN1X2 TSW 102 07 L S Samtec 11 2 ...

Page 8: ...RECIPIENT OF MATERIALS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE Skyworks products are not intended for use in medical lifesaving or life sustaining applications or other equipment in which the failure of the Skyworks products could lead to personal injury death physical or environmental damage Skyworks customers using or selling Skyworks products for use in such applications do so at the...

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