SiT6502EB HW UM Preliminary Rev 1.0
Page 8 of 33
SiT6502EB Evaluation Board (EVB) HW User Manual
3.
1.8V - Remove the Jumper.
9
I
2
C/SPI Mode Connection
The 10 pin Header J76 (
) is mainly used for configuring the SiT6503EB into I
2
C and SPI Mode
(I
2
C Mode is default one)
For I
2
C Mode of Operation:
1.
SCLK_OUT is shorted to SCLK in J76.
2.
SDAIO_OUT is shorted to SDAIO in J76.
3.
CSB_OUT is shorted to CSB in J76.
Figure 5. Supply Regulator for PLLs
For SPI Mode of Operation:
1.
SCLK_OUT is shorted to SCLK in J76.
2.
SDAIO_OUT is shorted to SDAIO in J76.
3.
CSB_OUT is shorted to CSB in J76.
4.
SDO_OUT is shorted to SDO in J76.
5.
JSCL1 Jumper should be removed.
6.
JVDD1 Jumper should be changed from (2 to 3) to (1 to 2).
7.
J73 Jumper should be changed from (1 to 2) to (2 to 3).
10
Clock Inputs
The SiT6502EB has eight inputs (4 differential pairs) with SMA connectors (IN0_P, IN0_N, IN1_P, IN1_N,
IN2_P, IN2_N, IN3_P, IN3_N) for receiving external clock signals. All input clocks are ac-coupled and
50
below. This represents four differential input clock pairs. Single-
