SiT6502EB HW UM Preliminary Rev 1.0
Page 9 of 33
SiT6502EB Evaluation Board (EVB) HW User Manual
ended clocks can be used by driving the ‘P’ side of the differential pair with the ‘N’ input floating.
shows the Input Clock Termination Circuit for one of the 4 pairs.
Figure 6. Input Clock Termination Circuit
11
Clock Outputs
When shipped from factory, each of the twenty output drivers (8 differential pairs) is ac-coupled to its
respective SMA connector – this is the default configuration. The output clock termination circuit is
shown in
below. If dc coupling is required, the corresponding 0.1 uF ac coupling capacitor can
be replaced with a zero
shows Output Clock Termination Circuit for one of the 8
output pairs.
