2
Interface
type
port D1
port D3
S3-1 S3-2 S3-3 S3-4
RS-485 2-w.
0
0
0
0
RS-485 4-w.
0
1
0
1
RS-422
1
0
1
0
Table 2. Choosing RS-485 interface types
using dip switch bank S3
Two-wire RS-485 mode uses the input terminals for
I/O. In older ADS/VAD units, for two-wire mode the
+ in and + out needed to be combined, as well as - in
and - out; old and new units can be used together with
the old-style cable layout.
Current loop output:
The RS-485 output impedance
of port D1 can be made suitable for digital 20 mA
current loop ('TTY') applications by pulling a 2-pin
jumper (C2-3) from the board, thus inserting a resistor
into the non-inverting data line. The jumper may be
put on pins C1-2 to save it.
Current loop I/O should
use only non-inverting lines and signal ground (see
figure 3); the interface type should be set to RS-485
(4-w). Input signal voltage on A-GND (IN+-GND)
should be at least 4V.
RS-485 line biasing:
In most cases, the RS-485 data
interface works with the default settings. If, however,
data line biasing is called for by other equipment
connected to the ADS 1200, biasing impedances may
need to be applied and dwell times set. With the other
dip switches configured for RS-485 mode, the
eightfold switch banks S1 (for interface D1) and S2
(for interface D3) on the ADS 1200 circuit boards
(figure 2) control attachment of two bias impedance
resistors to both input and inverting input (table 3
below).
Switch
bank S1 for D1
bank S2 for D3
Function (RS-485 mode set)
1-3
dwell time select, see table 4
4 ON
inverting input tied to +5V over 390
5 ON
inverting input tied to +5V over 10 k
6 ON
line termination 120
(default = off)
7 ON
input tied to GND over 10 k
8 ON
input tied to GND over 390
Table 3. Choosing bias resistances, dwell times and line
termination for interfaces D1 and D3
Note that the 'soft zero' biasing adaptation method
used ties the
inverting
('negative') input to the
higher voltage, while the biasing resistor of the
normal input is tied to signal ground. This provides
a well-defined bus state when no driver is active.
The first three dip switches of the banks S1 and S2
on the circuit boards (figure 3) are used to
configure the tristate-sensing/dwell timing of
interface D1 and D3, respectively, if biasing of
RS-485 lines is used, to help indicate the
conclusion of transmission (table 3). Dwell time is
approximately 10*bit length or slightly longer.
Setting
no.
Switch
bank S1 for D1
bank S2 for D3
Dwell
time
(±7%)
Data
rate
(bit/s)
1
2
3
0
OFF OFF OFF
*
0-max
1
OFF OFF
ON
**
0-max
2
OFF
ON
OFF
0.17 ms
64000
3
OFF
ON
ON
0.34 ms
38400
4
ON
OFF OFF
0.67 ms
19200
5
ON
OFF
ON
1.35 ms
9600
6
ON
ON
OFF
2.68 ms
4800
7
ON
ON
ON
5.38 ms
2400
*) default, hardware tri-state detect (1V differential sense,
not to be used together with line-biasing
)
**) logic high in the data directly drives the output enable
(i.e. no delay). This setting is especially suitable for
very low data rates.
Table 4. Dip switch settings for unbiased and biased
RS-485 interfacing. Settings 1-7 all need bias resistors
to define zero.
Depending on the actual data rate, switches 1-3 of
block S1 and S2 should then be set as per table 4
(
read the notes below
). Default is all three switches
off, i.e. hardware tristate sensing.
Notes on dwell times:
-
When in doubt about which of two dwell times to
select, use the longer of the two.
- Settings 1-7 only work if the lines are biased to a
‘soft zero’.
- The serial receiver dwell timing circuitry (re)starts
a timer on the rising edges of input data from the
copper side, at the same time sending an output
Figure 3. Current loop connections
U603
1
1
ON
S1
S2
S3
1
2
3
1
2
3
1
2
3
A
B
C
ADS TRX 650 2033 3
WWJJ
1
Figure 2. ADS TRA/B printed circuit board; details left out
for clarity.
Take care not to damage the optical fiber
floating above the board.
GND
B (IN-)
A (IN+)
GND
B (OUT-)
A (OUT+)
220 ohm,
internal
jumper removed
