SingMai Electronics
SB10 User Manual Revision 0.1
Page 9 of 29
Sheet 7.
Two clock sources for the PT4 are available.
The PT4 decoder requires a line locked clock. The first option to achieve this is a voltage controlled
crystal oscillator, with the frequency of the oscillator controlled using a PWM output from the PT4
IP core. This output, VCO_PWM, is filtered by R14 and C31 to provide an analogue voltage which is
buffered by U6. The resulting 0-3.3V control voltage adjusts the frequency of the crystal voltage
controlled oscillator (VCXO), X1. The adjustment range is approximately ±150ppm. The centre
frequency (1.65VDC control voltage) is 27.0MHz.
The output of the VCXO is then multiplied to 74.25MHz or 74.18MHz (this is for backward
compatibility to HD video) – selection is performed via the FREQ_SEL port. For the PT4 the clock
input is 74.25MHz which is then divided down in the FPGA to provide the 27MHz and 54MHz clocks
required by the PT4. The other clock mode is described in Sheet 8.
The ‘LOCK’ LED is driven from a port of the FPGA. It is lit when the PT4 decoder status indicates
that horizontal lock has been achieved and the input is a valid standard supported by the decoder.
U7 is a proprietary copy-protection IC. U7 calculates a checksum from a PT13 generated data
stream, and the calculated checksum from U7 is compared with an FPGA internally generated
checksum. If the two do not match the SB10 module is shut down. This means that even if the bit
stream of the FPGA/EEPROM is captured the SB10 will not run without U7 being fitted.
U17 is an RS232 level translator. The RS232 data interface is described in Chapter 3.
X2 provides a fixed 27MHz clock. This provides a stable clock to the microcontroller and also for
the DDS 150MHz clock.
Sheet 8.
Sheet 8 provides an alternative to the crystal lock (see Sheet 7) with a wider lock range. The PT4
decoder generates a sinewave of approximate 27MHz frequency. The sinewave is converted to
analogue by U23 and then filtered to remove clock components. The zero crossing point of this
waveform is then detected by U24 which then provides a digital 27MHz clock. The frequency of
this sinewave is then adjusted by the PT4 decoder until horizontal lock is achieved.
Sheet 9.
Sheet 9 permits data to be inserted into ther video stream (from receiver to transmitter). This
feature is not supported in the PT4.
Sheet 10.
U20 is the HDMI transmitter. The PT4 provides BT656 formatted data which drives the HDMI
transmitter directly. Control of the transmitter is provided by the FPGA via an I2C interface.
Sheet 11.
J9 is the HDMI connector. D3, D4 and D9 provide overshoot protection for the TDMS signals. D10
indicates if an HDMI receiver has been detected (hot plug detect).
