SingMai Electronics
SB10 User Manual Revision 0.1
Page 8 of 29
4.
Circuit description
Figures 3-13 show the schematics for the SB10. Below is a brief technical description of the SB10
module.
Sheet 1.
J3 is the 5VDC power input connector to the SB10 module. The 5VDC is protected from over-
voltage and reverse polarity inputs by D1, D2 and resettable fuse, F1. The input is then filtered by L1
and C2 to provide the ‘clean’ 5VDC for the analogue input stage and also linear regulated by U1 to
provide the 3.3VDC supply voltage.
Sheet 2.
U2 provides the 1.2VDC for the internal voltage of the FPGA. U3 provides the 2.5VDC for the
analogue PLL circuity of the FPGA and L2 and C25 filter the VCCINT for the FPGA PLL digital blocks.
U18 provides the 1.8V supply to the HDMI transmitter.
Sheet 3.
Sheet 3 is the analogue front end (AFE). The analogue video inputs, which may be NTSC or PAL,
may be either coaxial or twisted pair.
If twisted pair, they are terminated in 100Ω (R26) and converted from differential to single ended
outputs by U9. If coaxial inputs they are treated as a pseudo-differential input, with the ground
screen of the BNC input connector connected to ground via R25 and C61, which affords some hum
rejection for long cable runs. U15 converts this pseudo-differential input to a singled ended output
while U8 provides 6dB of gain to compensate for the attenuation in U15.
J6 selects either the differential or coaxial video input and J7 selects the mid-rail voltage offset
used by the AFE.
U10 is a voltage controlled amplifier. The PT4 decoder measures the amplitude of the
synchronizing signals and compares them to an internal reference: this amplifier compensates for
any loss in the input signal. U25 is not used in this application.
The output of U10 is AC coupled into U11A, which is a high input impedance, low input bias current
op-amp. The average DC level of video varies widely and to ensure it can be scaled into the
analogue to digital converter (ADC) properly it must be clamped. The AFE uses a sync tip clamp.
The most negative part of the AC coupled video is clamped to the VCLAMP reference voltage,
which is the most negative reference voltage of the ADC. The ADC requires a 0.5V to 2.5V (2V pk-
pk) input signal and the sync tips (the most negative part of the video signal) are clamped, using
‘ideal’ diode D5 and U11B, to the 0.5V ADC reference. The black level of the video (back porch
level) is measured and used to restore the video black level by the PT4 decoder.
Sheet 4.
U19 is a 10 bit, 80MHz ADC which is run at 54MHz. The ADC is used in single-ended mode. The
clamped video from U11A is applied to the VIN+ input, and VIN- input is biased to mid rail (1.5V).
U14 provides the ‘clean’ 3.0V supply for the ADC. The output of the ADC, ADC[9:0] is the straight
binary coded, digital composite video which is applied directly to the PT4 decoder.
Sheet 5.
U4 is the FPGA. The FPGA is an Altera EP4CE15 device in a 144 pin 0.5mm TQFP package. The FPGA
contains the PT4 NTSC/PAL decoder and a SingMai PT13 control microprocessor which also
provides the I2C control to the HDMI transmitter.
Sheet 6.
The FPGA is a volatile device and needs configuring on switch on, which it does using U5, a 4Mb
EEPROM. The device is automatically configured on switch on, and successful configuration is
indicated by LED, ‘FPGA OK’. The EEPROM may also be reprogrammed via J4, which is compatible
with the Altera ‘USB-Blaster’ and the Quartus Programmer.
