19. Appendix—Si3406-Non-ISO-FB Design and Layout Checklist
Although the EVB design is pre-configured as a Class 3 PD with 5 V output, the schematics and layouts can easily be adapted to meet
a wide variety of common output voltages and power levels.
The complete EVB design databases for the standard 5 V/Class 3 configuration are located at
www.silabs.com/PoE
link. Silicon Labs
strongly recommends using these EVB schematics and layout files as a starting point to ensure robust performance and avoid common
mistakes in the schematic capture and PCB layout processes.
Below is a recommended design checklist that can assist in trouble-free development of robust PD designs.
Refer also to the Si3406-non-ISO-FB data sheet and AN1130 when using the following checklist.
1. Design Planning checklist:
a. Determine if your design requires an isolated or non-isolated topology. For more information, see AN1130.
b. Silicon Labs strongly recommends using the EVB schematics and layout files as a starting point as you begin integrating the
Si3406-non-ISO-FB into your system design process.
c. Determine your load’s power requirements (i.e., VOUT and IOUT consumed by the PD, including the typical expected transi-
ent surge conditions). In general, to achieve the highest overall efficiency performance of the Si3406-non-isolated Flyback,
choose the highest output voltage option used in your PD and then post regulate to the lower supply rails, if necessary.
d. Based on your required PD power level, select the appropriate class resistor RCLASS value by referring to AN1130.
2. General Design checklist:
a. ESD caps (C12–C19 in
Figure 2.3 Si3406-Non-Isolated Flyback EVB Schematic: 5 V, Class 3 PD on page 4
) are strongly
recommended for designs where system-level ESD (IEC6100-4-2) must provide >15 kV tolerance.
b. If your design uses an AUX supply, be sure to include a 3 Ω surge limiting resistor in series with the AUX supply for hot inser-
tion. Refer to AN1130 when AUX supply is 48 V.
3. Layout Guidelines:
a. Make sure VNEG pin of the Si3406 is connected to the backside of the QFN package with an adequate thermal plane, as
noted in the data sheet and AN1130.
b. Keep the trace length from SWO to VSS as short as possible. Make all of the power (high current) traces as short, direct, and
thick as possible. It is a good practice on a standard PCB board to make the traces an absolute minimum of 15 mils (0.381
mm) per ampere.
c. Usually, one standard via handles 200 mA of current. If the trace needs to conduct a significant amount of current from one
plane to the other, use multiple vias.
d. Keep the circular area of the loop from the Switcher FET output to the inductor or transformer and returning from the input filter
capacitors (C1–C3) to VSS as small a diameter as possible. Also, minimize the circular area of the loop from the output of the
inductor or transformer to the Schottky diode and returning through the first stage output filter capacitor back to the inductor or
transformer as small as possible. If possible, keep the direction of current flow in these two loops the same.
e. Keep the high power traces as short as possible.
f. Keep the feedback and loop stability components as far from the transformer/inductor and noisy power traces as possible.
g. If the outputs have a ground plane or positive output plane, do not connect the high current carrying components and the filter
capacitors through the plane. Connect them together, and then connect to the plane at a single point.
To help ensure first-pass success, contact our customer support by submitting a help ticket and uploading your schematics and layout
files for review.
UG332: Class 3 Non-Isolated Evaluation Board for the Si3406
Appendix—Si3406-Non-ISO-FB Design and Layout Checklist
silabs.com
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