6.7.1 Verify Free-Run Mode Operation
Assuming an OCXO or TCXO output has been applied to the REF/REFb input(s) and no external clocks have been connected to the
INPUT CLOCK differential SMA connectors (labeled "INx/INxB"), located around the perimeter of the EVB, the DUT should now be op-
erating in free-run mode. The DUT will be locked to the OCXO/TCXO in this case.
You can run a quick check to determine if the device is powered up and generating output clocks (and consuming power) by clicking on
the Read All button highlighted above and then reviewing the voltage, current and power readings for each VDDx supply.
Note:
Shutting the VDD and VDDA supplies Off and then On will power-down and reset the DUT. Every time you do this, to reload the
Silicon Labs-created default plan into the DUT's register space, you must go back to the Wizard's main menu and select "Write Design
to EVB":
Figure 6.10. Write Design to EVB
Failure to do the step above will cause the device to read in a preprogrammed plan from its non-volatile memory (NVM). How-
ever, the plan loaded from the NVM may not be the latest plan recommended by Silicon Labs for evaluation.
At this point, you should verify the presence and frequencies of the output clocks (running to free-run modes from the crystal) using
appropriate external instrumentation connected to the output clock SMA connectors. To verify the output clocks are toggling at the cor-
rect frequency and signal format, click on View Design Report as highlighted below.
UG256: Si5383 Evaluation Board User's Guide
Using the Si5383 EVB and Installing ClockBuilder Pro (CB Pro) Desktop Software
silabs.com
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