5. Clock Input and Output Circuits
5.1 Clock Input Circuits (REF/REFB, IN0/IN0B-IN2/IN2B, IN3, IN4)
The Si5348-E-EVB has eight SMA connectors (REF/REFB, IN0/IN0B–IN2/IN2B) for receiving external differential clock signals. The
REF/REFB differential input clock is intended to support a TCXO or OCXO, such as the included SiOCXO1-EB or the included SiTC-
XO1-EB, which determines the Si5348’s wander performance. (Please note that this input clock is different from the optional reference
clock that may be applied at XA/XB.) All differential input clocks are terminated as shown in the figure below. The only exception is that
the terminating 49.9 Ω resistor for REF is not installed. This is R84 corresponding to IN0's R76 in the figure below. The reason for this
exception is that single-ended TCXOs and OCXOs typically cannot drive a 50 Ω load. Note that input clocks are ac-coupled and 50 Ω
terminated. This represents four differential input clock pairs. Single-ended clocks can be used by appropriately driving one side of the
differential pair with a single-ended clock. For details on how to configure inputs as single-ended, please refer to the Si5348 data sheet
or reference manual.
Figure 5.1. Differential Input Clock Termination Circuit
In addition, the Si5348-E-EVB supports two SMA connectors (IN3, IN4) for receiving external single-ended LVCMOS clocks. Each of
these clocks connects to its respective Si5348 pins via a single installed 0 Ω resistor. There are no other termination components on
the EVB.
UG362: Si5348-E Evaluation Board User's Guide
Clock Input and Output Circuits
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