Si5340-EVB
10
Rev. 1.0
Verify Free-Run Mode Operation
Assuming no external clocks have been connected to the INPUT CLOCK differential SMA connectors (labeled
"INx/INxB") located around the perimeter of the EVB, the DUT should now be operating in free-run mode, as the
DUT will be locked to the crystal in this case.
You can run a quick check to determine if the device is powered up and generating output clocks (and consuming
power) by clicking on the
Read All
button (the bottom-right of Figure 14) and then reviewing the voltage, current,
and power readings for each VDDx supply.
Note:
Shutting the VDD and VDDA power supplies "Off" and then "On" will power-down and reset the DUT. Every time you do
this, to reload the Silicon Labs-created default plan into the DUT's register space, you must go back to the Wizard's main
menu and select
Write Design to EVB
:
Figure 15. Write Design to EVB
Failure to do the step above will cause the device to read in a pre-programmed plan from its non-volatile memory (NVM).
However, the plan loaded from the NVM may not be the latest plan recommended by Silicon Labs for evaluation.
At this point, you should verify the presence and frequencies of the output clocks (running in free-run mode from
the crystal) using appropriate external instrumentation connected to the output clock SMA connectors. To verify the
output clocks are toggling at the correct frequency and signal format, click on
View Design Report
as highlighted
in Figure 16.
Figure 16. View Design Report
